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rename missing vcs/verilator names | fix ci path

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abejgonzalez
2019-07-16 21:36:36 -07:00
parent 52f959f457
commit b7bc96b6d6
8 changed files with 14 additions and 45 deletions
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2
sims/verilator/Makefile
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@@ -92,7 +92,7 @@ $(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk
#########################################################################################
# create a verisim vpd rule
# create a verilator vpd rule
#########################################################################################
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
rm -f $@.vcd && mkfifo $@.vcd