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Merge pull request #1667 from ucb-bar/llc-buffers

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Add cfg fragment to insert LLC interior/exterior buffers
This commit is contained in:
Jerry Zhao
2023-11-17 14:27:04 -08:00
committed by GitHub
parent 846c8563fc 1e2667e0bc
commit b84841704a
1 changed files with 12 additions and 1 deletions
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13
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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@@ -1,8 +1,9 @@
package chipyard.config
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper, InclusiveCacheKey}
import freechips.rocketchip.diplomacy.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
// Replaces the L2 with a broadcast manager for maintaining coherence
class WithBroadcastManager extends Config((site, here, up) => {
@@ -16,3 +17,13 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
case DTSTimebase => freqMHz
})
// Adds buffers on the interior of the inclusive LLC, to improve PD
class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
})
// Adds buffers on the exterior of the inclusive LLC, to improve PD
class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
})