Get topAnnos into the mix
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@@ -27,12 +27,6 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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case _ => None
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}.toList
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// order is determined by DependencyAPIMigration
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val topTransforms = Seq(
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new ReParentCircuit,
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new RemoveUnusedModules
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)
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lazy val rootCircuitTarget = CircuitTarget(harnessTop.get)
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val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++
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@@ -65,10 +59,14 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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// Top Generation
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def executeTop(): Seq[ExtModule] = {
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val annos = new FirrtlStage().execute(Array.empty, annotations ++ Seq(
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RunFirrtlTransformAnnotation(Dependency[ReParentCircuit]),
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RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules])
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))
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val annos = new FirrtlStage().execute(
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Array.empty,
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annotations ++ Seq(
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RunFirrtlTransformAnnotation(Dependency[ReParentCircuit]),
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RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules])
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) ++
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topAnnos
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)
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annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
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case Some(circuit) =>
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dump(circuit, annos, topFir, topAnnoOut)
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