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Get topAnnos into the mix

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chick
2021-02-16 16:29:41 -08:00
parent 7c2d7abbe1
commit bbc8800840
1 changed files with 8 additions and 10 deletions
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18
tapeout/src/main/scala/barstools/tapeout/transforms/GenerateTopAndHarness.scala
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@@ -27,12 +27,6 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
case _ => None case _ => None
}.toList }.toList
// order is determined by DependencyAPIMigration
val topTransforms = Seq(
new ReParentCircuit,
new RemoveUnusedModules
)
lazy val rootCircuitTarget = CircuitTarget(harnessTop.get) lazy val rootCircuitTarget = CircuitTarget(harnessTop.get)
val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++ val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++
@@ -65,10 +59,14 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
// Top Generation // Top Generation
def executeTop(): Seq[ExtModule] = { def executeTop(): Seq[ExtModule] = {
val annos = new FirrtlStage().execute(Array.empty, annotations ++ Seq( val annos = new FirrtlStage().execute(
RunFirrtlTransformAnnotation(Dependency[ReParentCircuit]), Array.empty,
RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules]) annotations ++ Seq(
)) RunFirrtlTransformAnnotation(Dependency[ReParentCircuit]),
RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules])
) ++
topAnnos
)
annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match { annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
case Some(circuit) => case Some(circuit) =>
dump(circuit, annos, topFir, topAnnoOut) dump(circuit, annos, topFir, topAnnoOut)