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This commit is contained in:
abejgonzalez
2022-10-08 10:48:45 -07:00
committed by joey0320
parent ca88bf5a2f
commit c179f53ed0
2 changed files with 2 additions and 2 deletions
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2
sims/vcs/Makefile
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@@ -32,7 +32,7 @@ default: $(sim)
debug: $(sim_debug) debug: $(sim_debug)
######################################################################################### #########################################################################################
# simulaton requirements # simulation requirements
######################################################################################### #########################################################################################
SIM_FILE_REQS += \ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v

2
sims/verilator/Makefile
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@@ -50,7 +50,7 @@ SIM_FILE_REQS += \
$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
# the following files are needed for emulator.cc to compile (even if they aren't included in RTL) # the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build)
SIM_FILE_REQS += \ SIM_FILE_REQS += \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \