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Fix VCS

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This commit is contained in:
abejgonzalez
2022-10-08 10:45:31 -07:00
committed by joey0320
parent a384fa9d1d
commit ca88bf5a2f
2 changed files with 3 additions and 4 deletions
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4
sims/vcs/Makefile
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@@ -67,11 +67,11 @@ model_dir_debug = $(build_dir)/$(long_name).debug
#########################################################################################
# vcs simulator rules
#########################################################################################
$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
$(sim): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
rm -rf $(model_dir)
$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir)
$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
$(sim_debug): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug) \
+define+DEBUG -debug_access+all -kdb -lca

3
vcs.mk
View File

@@ -51,8 +51,7 @@ VCS_NONCC_OPTS = \
-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-debug_pp \
+incdir+$(build_dir) \
$(sim_vsrcs)
+incdir+$(build_dir)
PREPROC_DEFINES = \
+define+VCS \