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Update rocket-chip with modern diplomacy/prci packaging

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This commit is contained in:
Jerry Zhao
2024-06-06 11:00:24 -07:00
parent 2a9fe9bb67
commit c1b869dfc0
24 changed files with 23 additions and 25 deletions
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2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: cdf3db20f0...2d36b0ab43

3
fpga/src/main/scala/vc707/Configs.scala
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@@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.tile.{XLen}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}

3
fpga/src/main/scala/vcu118/Configs.scala
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@@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.tile.{XLen}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}

2
generators/boom

Submodule generators/boom updated: 41c8fc9bdf...6a3ad0a1d9

2
generators/chipyard/src/main/scala/SpikeTile.scala
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@@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.tile._ import freechips.rocketchip.tile._
import freechips.rocketchip.prci.ClockSinkParameters import freechips.rocketchip.prci._
case class SpikeCoreParams() extends CoreParams { case class SpikeCoreParams() extends CoreParams {
val useVM = true val useVM = true

1
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------ // ------------------------------
// Configs with MMIO accelerators // Configs with MMIO accelerators

1
generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------------------------------------ // ------------------------------------------------------------
// Configs which demonstrate modifying the uncore memory system // Configs which demonstrate modifying the uncore memory system

1
generators/chipyard/src/main/scala/config/NoCConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{SBUS, MBUS} import freechips.rocketchip.subsystem.{SBUS, MBUS}
import constellation.channel._ import constellation.channel._

1
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{MBUS} import freechips.rocketchip.subsystem.{MBUS}
// --------------------------------------------------------- // ---------------------------------------------------------

1
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------ // ------------------------------
// Configs with RoCC Accelerators // Configs with RoCC Accelerators

2
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -1,7 +1,7 @@
package chipyard package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.prci.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{InCluster} import freechips.rocketchip.subsystem.{InCluster}
// -------------- // --------------

2
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
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@@ -7,7 +7,7 @@ import chisel3.util.{log2Up}
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.prci.{AsynchronousCrossing}
import chipyard.stage.phases.TargetDirKey import chipyard.stage.phases.TargetDirKey
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.tile.{XLen}

2
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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@@ -2,7 +2,7 @@ package chipyard.config
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{DTSTimebase} import freechips.rocketchip.resources.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters} import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
// Replaces the L2 with a broadcast manager for maintaining coherence // Replaces the L2 with a broadcast manager for maintaining coherence

2
generators/chipyard/src/main/scala/example/TutorialTile.scala
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@@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.tile._ import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci.ClockSinkParameters import freechips.rocketchip.prci._
// Example parameter class copied from CVA6, not included in documentation but for compile check only // Example parameter class copied from CVA6, not included in documentation but for compile check only
// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure

2
generators/constellation

Submodule generators/constellation updated: 6664839b10...5c9d27359d

2
generators/cva6

Submodule generators/cva6 updated: 9d1c106834...de4772f1d6

5
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -12,7 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing} import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig} import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
import testchipip.cosim.{TracePortKey, TracePortParams} import testchipip.cosim.{TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -383,4 +384,4 @@ class FireSimLargeBoomSV39CospikeConfig extends Config(
new WithDefaultMemModel ++ new WithDefaultMemModel ++
new WithFireSimConfigTweaks++ new WithFireSimConfigTweaks++
new chipyard.config.WithSV39 ++ new chipyard.config.WithSV39 ++
new chipyard.LargeBoomV3Config) new chipyard.LargeBoomV3Config)

2
generators/ibex

Submodule generators/ibex updated: 89c19c2d7b...8a43aa70da

2
generators/icenet

Submodule generators/icenet updated: 969bc8f9a0...6fd35bf5a2

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: ca0431493e...732cbe1990

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 3cec0f0dee...4ac1529d98

2
generators/shuttle

Submodule generators/shuttle updated: 4792a1aba4...799263c618

2
generators/testchipip

Submodule generators/testchipip updated: 7a30dc737d...b85f5ac046

2
tools/rocket-dsp-utils

Submodule tools/rocket-dsp-utils updated: c4c638da02...6ee2309f80