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Co-Authored-By: Abraham Gonzalez <abe.j.gonza@gmail.com>
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Jerry Zhao
2019-09-26 21:06:57 -07:00
parent 63a1315f33
commit c2547bd04f
1 changed files with 9 additions and 9 deletions
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18
docs/Generators/Top-Testharness.rst
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@@ -21,14 +21,14 @@ The ``BaseSubsystem`` is defined in ``generators/rocketchip/src/main/scala/subsy
Subsystem
^^^^^^^^^^^^^^^^^^^^^^^^^
Looking in ``generators/utilities/src/main/scala/Subsystem.scala``, we can see how Chipyard extends the ``BaseSubsystem`` abstract class. The ``HasBoomAndRocketTiles`` trait defines and instantiates BOOM or Rocket tiles, depending on the parameters specified. We also connect connect some basic IOs for each tile here, specifically the hartids and the reset vector.
Looking in ``generators/utilities/src/main/scala/Subsystem.scala``, we can see how Chipyard's ``Subsystem`` extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that defines and instantiates BOOM or Rocket tiles, depending on the parameters specified. We also connect some basic IOs for each tile here, specifically the hartids and the reset vector.
System
^^^^^^^^^^^^^^^^^^^^^^^^^
``generators/utilities/src/main/scala/System.scala`` completes the definition of the System.
``generators/utilities/src/main/scala/System.scala`` completes the definition of the ``System``.
- ``HasHierarchicalBusTopology`` is defined in Rocket Chip, and specifies connections between the top-level buses.
- ``HasHierarchicalBusTopology`` is defined in Rocket Chip, and specifies connections between the top-level buses
- ``HasAsyncExtInterrupts`` and ``HasExtInterruptsModuleImp`` adds IOs for external interrupts and wires them appropriately to tiles
- ``CanHave...AXI4Port`` adds various Master and Slave AXI4 ports, adds TL-to-AXI4 converters, and connects them to the appropriate buses
- ``HasPeripheryBootROM`` adds a BootROM device
@@ -38,24 +38,24 @@ Tops
A SoC Top then extends the ``System`` class with any config-specific components. There are two "classes" of Tops in Chipyard.
- ``Top`` is the default setup. These top modules instantiate a serial module which interfaces with the TestHarness. In addition, the debug module interface is tied off. All other example "Tops" (except the ``TopWithDTM``) extend this Top as the "base"
- ``Top`` is the default setup. These top modules instantiate a serial module which interfaces with the ``TestHarness``. In addition, the debug module interface is tied off. All other example "Tops" (except the ``TopWithDTM``) extend this Top as the "base" top-level system.
- ``TopWithDTM`` does not include the serial module, and the debug module interface (DMI) is left available. This Top is used for DTM-based bringup.
For a custom Top, for example the ``TopWithGPIO``, a mixed-in trait adds the additional modules or IOs.
For a custom Top a mixed-in trait adds the additional modules or IOs (an example of this is ``TopWithGPIO``).
TestHarness
-------------------------
There are two variants of ``TestHarness`` generators in Chipyard, both located in ``generators/example/src/main/scala/TestHarness.scala``. One is designed for TSI-based bringup, while the other performs DTM-based bringup. See TODO for more information on these two methodologies.
There are two variants of ``TestHarness`` generators in Chipyard, both located in `generators/example/src/main/scala/TestHarness.scala <https://github.com/ucb-bar/chipyard/blob/master/generators/example/src/main/scala/TestHarness.scala>`__ . One is designed for TSI-based bringup, while the other performs DTM-based bringup. See TODO for more information on these two methodologies.
The wiring between the ``TestHarness`` and the Top are performed in methods defined in mixins added to the Top. When these methods are called from the TestHarness, they may instantiate modules within the scope of the harness, and then connect them to the dut. For example, the ``connectSimAXIMem`` method defined in the ``CanHaceMasterAXI4MemPortModuleImp`` trait, when called from the TestHarness, will instantiate SimAXIMems and connect them to the correct IOs of the top.
The wiring between the ``TestHarness`` and the Top are performed in methods defined in mixins added to the Top. When these methods are called from the TestHarness, they may instantiate modules within the scope of the harness, and then connect them to the dut. For example, the ``connectSimAXIMem`` method defined in the ``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the TestHarness, will instantiate SimAXIMems and connect them to the correct IOs of the top.
While this roundabout way of attaching to the IOs of the top may see unnecessarily complex, it allows the designer to compose custom traits together without having to worry about the details of the implementation of any particular trait.
While this roundabout way of attaching to the IOs of the top may seem to be unnecessarily complex, it allows the designer to compose custom traits together without having to worry about the details of the implementation of any particular trait.
Specifying a Top
^^^^^^^^^^^^^^^^^^^^^^^^^
To see why the Top connection method is useful, consider the case where we want to use a custom Top with additional GPIO pins. In ``generators/example/src/main/scala/Top.scala``, we can see how the ``TopWithGPIO`` class adds the ``HasPeripheryGPIO`` trait. This trait adds IOs to the top module, instantiates a TileLink GPIO node, and connects it to the proper buses.
To see why the Top connection method is useful, consider the case where we want to use a custom Top with additional GPIO pins. In `generators/example/src/main/scala/Top.scala <https://github.com/ucb-bar/chipyard/blob/master/generators/example/src/main/scala/Top.scala>`__ , we can see how the ``TopWithGPIO`` class adds the ``HasPeripheryGPIO`` trait. This trait adds IOs to the Top module, instantiates a TileLink GPIO node, and connects it to the proper buses.
If we look at the ``WithGPIOTop`` mixin in the ``ConfigMixins.scala`` file, we see that adding this mixin to the top-level Config overrides the ``BuildTop`` key with a custom function that both instantiates the custom Top, and drives all the GPIO pins. When the ``TestHarness`` looksup the ``BuildTop`` key, this function will run and perform this wiring, and then return the Top module.