Merge pull request #127 from tymcauley/use-scala-2.13

Update scala/sbt/chisel versions, fix CI

build.sbt

@@ -1,15 +1,14 @@
 // See LICENSE for license details.
 
 val defaultVersions = Map(
-  "chisel3" -> "3.5.1",
-  "chisel-iotesters" -> "2.5.1"
+  "chisel3" -> "3.5.5",
+  "chisel-iotesters" -> "2.5.5"
 )
 
 organization := "edu.berkeley.cs"
 version := "0.4-SNAPSHOT"
 name := "tapeout"
-scalaVersion := "2.12.13"
-crossScalaVersions := Seq("2.12.13", "2.13.6")
+scalaVersion := "2.13.10"
 scalacOptions := Seq("-deprecation", "-feature", "-language:reflectiveCalls")
 Test / scalacOptions ++= Seq("-language:reflectiveCalls")
 fork := true

project/build.properties

@@ -1 +1 @@
-sbt.version=1.3.13
+sbt.version=1.8.2

src/main/scala/barstools/tapeout/transforms/ExtraTransforms.scala

@@ -14,7 +14,7 @@ class ExtraLowTransforms extends Transform with DependencyAPIMigration {
   // this PropagatePresetAnnotations is needed to run the RemoveValidIf pass (that is removed from CIRCT).
   // additionally, since that pass isn't explicitly a prereq of the LowFormEmitter it
   // needs to wrapped in this xform
-  override def prerequisites:          Seq[TransformDependency] = Forms.LowForm :+
+  override def prerequisites: Seq[TransformDependency] = Forms.LowForm :+
     Dependency[firrtl.transforms.PropagatePresetAnnotations]
   override def optionalPrerequisites:  Seq[TransformDependency] = Forms.LowFormOptimized
   override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters

src/main/scala/barstools/tapeout/transforms/GenerateModelStageMain.scala

@@ -36,13 +36,16 @@ private class GenerateModelStageMain(annotations: AnnotationSeq) extends LazyLog
   }
 
   def executeStageMain(): Unit = {
-    val appendedAnnotations = annotations.filter(_ match {
-      case CompilerNameAnnotation(_) => true
-      case _ => false
-    }).map(_ match {
-      case CompilerNameAnnotation("low") => Some(RunFirrtlTransformAnnotation(Dependency[ExtraLowTransforms]))
-      case _ => None
-    }).flatten
+    val appendedAnnotations = annotations
+      .filter(_ match {
+        case CompilerNameAnnotation(_) => true
+        case _                         => false
+      })
+      .map(_ match {
+        case CompilerNameAnnotation("low") => Some(RunFirrtlTransformAnnotation(Dependency[ExtraLowTransforms]))
+        case _                             => None
+      })
+      .flatten
     val annos = new FirrtlStage().execute(Array.empty, annotations ++ appendedAnnotations)
 
     annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {

src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala

@@ -38,8 +38,7 @@ object DuplicateCompilerAnnotation extends HasShellOptions {
       longOption = "duplicate-compiler",
       shortOption = Some("DX"),
       toAnnotationSeq = (s: String) => {
-        Seq(
-          CompilerNameAnnotation(s))
+        Seq(CompilerNameAnnotation(s))
       },
       helpText = "duplicate-compiler",
       helpValueName = Some("same as --compiler FIRRTL flag")

src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala

@@ -1,50 +0,0 @@
-// See LICENSE for license details.
-
-package barstools.tapeout.transforms
-
-import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
-import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
-import org.scalatest.freespec.AnyFreeSpec
-import org.scalatest.matchers.should.Matchers
-
-class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
-  val io = IO(new Bundle {
-    val out = Output(UInt(32.W))
-  })
-
-  val r = RegInit(0.U)
-
-  io.out := r
-
-  invert(this)
-}
-
-class ResetNSpec extends AnyFreeSpec with Matchers {
-  "Inverting reset needs to be done throughout module in Chirrtl" in {
-    val chirrtl = (new ChiselStage)
-      .emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", "test_run_dir/reset_n_spec"))
-    chirrtl should include("input reset :")
-    (chirrtl should not).include("input reset_n :")
-    (chirrtl should not).include("node reset = not(reset_n)")
-  }
-
-  "Inverting reset needs to be done throughout module when generating firrtl" in {
-    // generate low-firrtl
-    val firrtl = (new ChiselStage)
-      .execute(
-        Array("-X", "low", "--target-dir", "test_run_dir/reset_inverting_spec"),
-        Seq(ChiselGeneratorAnnotation(() => new ExampleModuleNeedsResetInverted))
-      )
-      .collect {
-        case EmittedFirrtlCircuitAnnotation(a) => a
-        case EmittedFirrtlModuleAnnotation(a)  => a
-      }
-      .map(_.value)
-      .mkString("")
-
-    firrtl should include("input reset_n :")
-    firrtl should include("node reset = not(reset_n)")
-    (firrtl should not).include("input reset :")
-  }
-}