Fix Verilog Prerequisites + Ignore mv stdout (#1406)
* Fix Ibex vlog compilation deps | Ignore mv stderr * Init DRAMSim2 * Use size_t in cospike.cc * Use size_t in spiketile.cc
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@@ -57,6 +57,7 @@ HELP_COMMANDS += \
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# see HELP_COMPILATION_VARIABLES
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#########################################################################################
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include $(base_dir)/generators/cva6/cva6.mk
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include $(base_dir)/generators/ibex/ibex.mk
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include $(base_dir)/generators/tracegen/tracegen.mk
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include $(base_dir)/generators/nvdla/nvdla.mk
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include $(base_dir)/tools/dromajo/dromajo.mk
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@@ -174,7 +175,7 @@ MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVar
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# hack: lower to low firrtl if Fixed types are found
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# hack: when using dontTouch, io.cpu annotations are not removed by SFC,
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# hence we remove them manually by using jq before passing them to firtool
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$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
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$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(VLOG_SOURCES)
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ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
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$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
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$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
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@@ -191,7 +192,7 @@ endif
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if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
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$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
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$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
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$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
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rm -rf $(GEN_COLLATERAL_DIR)
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$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
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--no-dedup \
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@@ -204,7 +205,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE
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--allow-unrecognized-annotations \
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-X $(SFC_LEVEL) \
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$(EXTRA_FIRRTL_OPTIONS))
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-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
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-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL
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@if [ $(SFC_LEVEL) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json; fi
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@if [ $(SFC_LEVEL) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
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@if [ $(SFC_LEVEL) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
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@@ -226,7 +227,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE
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--split-verilog \
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-o $(GEN_COLLATERAL_DIR) \
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$(SFC_FIRRTL_FILE)
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-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF)
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-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null
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$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
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# DOC include end: FirrtlCompiler
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@@ -70,7 +70,7 @@ extern "C" void cospike_cosim(long long int cycle,
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if (!sim) {
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printf("Configuring spike cosim\n");
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std::vector<mem_cfg_t> mem_cfg;
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std::vector<int> hartids;
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std::vector<size_t> hartids;
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mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size));
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for (int i = 0; i < info->nharts; i++)
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hartids.push_back(i);
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@@ -75,7 +75,7 @@ public:
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void dcache_d(uint64_t sourceid, uint64_t data[8], unsigned char has_data, unsigned char grantack);
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void drain_stq();
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bool stq_empty() { return st_q.size() == 0; };
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~chipyard_simif_t() { };
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chipyard_simif_t(size_t icache_ways,
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size_t icache_sets,
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@@ -262,7 +262,7 @@ extern "C" void spike_tile(int hartid, char* isa,
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endianness_little,
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pmpregions,
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std::vector<mem_cfg_t>(),
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std::vector<int>(),
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std::vector<size_t>(),
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false,
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0);
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processor_t* p = new processor_t(isa_parser,
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@@ -488,7 +488,7 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) {
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}
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}
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}
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if (!found) {
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return false;
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}
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@@ -576,7 +576,7 @@ bool chipyard_simif_t::handle_cache_access(reg_t addr, size_t len,
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}
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}
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}
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#define SETIDX(ADDR) ((ADDR >> 6) & (n_sets - 1))
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uint64_t setidx = SETIDX(addr);
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uint64_t offset = addr & (64 - 1);
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Submodule generators/ibex updated: 5a512227d8...626127f229
@@ -113,6 +113,7 @@ fi
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echo '==> Installing DRAMSim2 Shared Library'
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cd $RDIR
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git submodule update --init tools/DRAMSim2
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cd tools/DRAMSim2
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make libdramsim.so
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cp libdramsim.so $RISCV/lib/
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