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Merge remote-tracking branch 'upstream/main' into graphics

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This commit is contained in:
Hansung Kim
2023-05-05 14:40:55 -07:00
parent 9301243a03 b8ccb7d4f6
commit c9762296ca
126 changed files with 2270 additions and 1280 deletions
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3
.github/scripts/defaults.sh vendored
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@@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -53,6 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"

6
.gitmodules vendored
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@@ -73,9 +73,6 @@
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git
[submodule "tools/rocket-dsp-utils"]
path = tools/rocket-dsp-utils
url = https://github.com/ucb-bar/rocket-dsp-utils
@@ -121,3 +118,6 @@
[submodule "generators/mempress"]
path = generators/mempress
url = https://github.com/ucb-bar/mempress.git
[submodule "tools/cde"]
path = tools/cde
url = https://github.com/chipsalliance/cde.git

33
build.sbt
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@@ -62,7 +62,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
new Group(test.name, Seq(test), SubProcess(options))
} toSeq
val chiselVersion = "3.5.5"
val chiselVersion = "3.5.6"
lazy val chiselSettings = Seq(
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
@@ -102,18 +102,8 @@ lazy val rocketMacros = (project in rocketChipDir / "macros")
)
)
lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
.settings(commonSettings)
.settings(
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
)
)
lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.dependsOn(hardfloat, rocketMacros, rocketConfig)
.dependsOn(hardfloat, rocketMacros, cde)
.settings(commonSettings)
.settings(chiselSettings)
.settings(
@@ -149,7 +139,12 @@ lazy val chipyard = (project in file("generators/chipyard"))
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation, mempress)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
.settings(
libraryDependencies ++= Seq(
"org.reflections" % "reflections" % "0.10.2"
)
)
.settings(commonSettings)
lazy val mempress = (project in file("generators/mempress"))
.dependsOn(rocketchip, midasTargetUtils)
@@ -246,16 +241,12 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
"org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
))
lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance"))
.settings(
commonSettings,
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.0.+" % "test",
"org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
))
lazy val cde = (project in file("tools/cde"))
.settings(commonSettings)
.settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip")
lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
.dependsOn(rocketchip, `api-config-chipsalliance`, dsptools)
.dependsOn(rocketchip, cde, dsptools)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

24
common.mk
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@@ -50,7 +50,7 @@ HELP_COMMANDS += \
" run-tests = run all assembly and benchmark tests" \
" launch-sbt = start sbt terminal" \
" {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \
" find-config-fragments = list all config. fragments and their locations (recursive up to CONFIG_FRAG_LEVELS=$(CONFIG_FRAG_LEVELS))"
" find-config-fragments = list all config. fragments"
#########################################################################################
# include additional subproject make fragments
@@ -231,7 +231,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIR
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
# DOC include end: FirrtlCompiler
$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST)
$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST)
$(base_dir)/scripts/split-module-files.py \
--model-hier-json $(MFC_MODEL_HRCHY_JSON) \
--dut $(TOP) \
@@ -243,6 +243,14 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
$(SED) -i 's/\.\///' $(TOP_MODS_FILELIST)
$(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST)
$(SED) -i 's/\.\///' $(BB_MODS_FILELIST)
$(base_dir)/scripts/uniqify-module-names.py \
--top-filelist $(TOP_MODS_FILELIST) \
--mod-filelist $(MODEL_MODS_FILELIST) \
--gen-collateral-path $(GEN_COLLATERAL_DIR) \
--model-hier-json $(MFC_MODEL_HRCHY_JSON) \
--out-model-hier-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \
--dut $(TOP) \
--model $(MODEL)
sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST)
$(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE)
@@ -253,10 +261,10 @@ $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_T
--out-top-bb-f $(TOP_BB_MODS_FILELIST) \
--out-model-bb-f $(MODEL_BB_MODS_FILELIST)
$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON)
$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED)
$(base_dir)/scripts/split-mems-conf.py \
--in-smems-conf $(MFC_SMEMS_CONF) \
--in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON) \
--in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \
--dut-module-name $(TOP) \
--model-module-name $(MODEL) \
--out-dut-smems-conf $(TOP_SMEMS_CONF) \
@@ -406,13 +414,9 @@ define \n
endef
CONFIG_FRAG_LEVELS ?= 3
.PHONY: find-config-fragments
find-config-fragments: private IN_F := $(shell mktemp -d -t cy-XXXXXXXX)/scala_files.f
find-config-fragments: $(SCALA_SOURCES)
@$(foreach file,$(SCALA_SOURCES),echo $(file) >> $(IN_F)${\n})
$(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) $(IN_F)
@rm -rf $(dir $(IN_F))
find-config-fragments:
$(call run_scala_main,chipyard,chipyard.ConfigFinder,)
.PHONY: help
help:

2
conda-reqs/chipyard.yaml
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@@ -103,7 +103,7 @@ dependencies:
- sty
- open_pdks.sky130a
- pip:
- hammer-vlsi[asap7]==1.1.0
- hammer-vlsi[asap7]==1.1.1
# doc requirements
- sphinx

1037
conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml generated
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File diff suppressed because it is too large Load Diff

1044
conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml generated
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File diff suppressed because it is too large Load Diff

3
docs/Customization/Keys-Traits-Configs.rst
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@@ -79,5 +79,4 @@ We can use this config fragment when composing our configs.
Chipyard Config Fragments
-------------------------
For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments
(config. fragments that match "class NAME extends CONFIG\n" on a single line and a subset of their children) and their file path in a fully initialized Chipyard repository.
For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments.

2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: 474ad19113...b6cd1bb7fe

4
fpga/src/main/scala/arty/Configs.scala
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@@ -1,7 +1,7 @@
// See LICENSE for license details.
package chipyard.fpga.arty
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
@@ -17,9 +17,9 @@ import chipyard.{BuildSystem}
// DOC include start: AbstractArty and Rocket
class WithArtyTweaks extends Config(
new WithArtyResetHarnessBinder ++
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithArtyResetHarnessBinder ++
new WithDebugResetPassthrough ++
new chipyard.config.WithDTSTimebase(32768) ++

13
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -2,7 +2,7 @@ package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
import freechips.rocketchip.jtag.{JTAGIO}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
@@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
import chipyard.iobinders.JTAGChipIO
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
require(ports.size == 2)
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
val resetPorts = ports.collect { case b: Bool => b }
require(resetPorts.size == 2)
withClockAndReset(th.clock_32MHz, th.ck_rst) {
// Debug module reset
th.dut_ndreset := ports(0)
th.dut_ndreset := resetPorts(0)
// JTAG reset
ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
}
}
})
@@ -63,6 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
io_jtag.TMS.i.po.map(_ := DontCare)
io_jtag.TDO.i.po.map(_ := DontCare)
}
case b: Bool =>
}
}
})

4
fpga/src/main/scala/arty/IOBinders.scala
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@@ -3,12 +3,12 @@ package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
import chipyard.iobinders.{ComposeIOBinder}
class WithDebugResetPassthrough extends ComposeIOBinder({
(system: HasPeripheryDebugModuleImp) => {
(system: HasPeripheryDebug) => {
// Debug module reset
val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
io_ndreset := system.debug.get.ndreset

2
fpga/src/main/scala/arty/TestHarness.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}

2
fpga/src/main/scala/arty100t/Configs.scala
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@@ -1,7 +1,7 @@
// See LICENSE for license details.
package chipyard.fpga.arty100t
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._

2
fpga/src/main/scala/arty100t/Harness.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.arty100t
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
import sifive.fpgashells.shell.xilinx._

1
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -2,7 +2,6 @@ package chipyard.fpga.arty100t
import chisel3._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}

2
fpga/src/main/scala/vc707/Configs.scala
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@@ -2,7 +2,7 @@ package chipyard.fpga.vc707
import sys.process._
import freechips.rocketchip.config.{Config, Parameters}
import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}

2
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode}
import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}

2
fpga/src/main/scala/vcu118/Configs.scala
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@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118
import sys.process._
import freechips.rocketchip.config.{Config, Parameters}
import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}

2
fpga/src/main/scala/vcu118/CustomOverlays.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118
import chisel3._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters, Field}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
import sifive.fpgashells.shell._

2
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode}
import sifive.fpgashells.shell.xilinx._

2
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup
import math.min
import freechips.rocketchip.config.{Config, Parameters}
import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._

2
fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.experimental.{attach}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters, Field}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
import sifive.fpgashells.shell._

2
fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
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@@ -4,7 +4,7 @@ import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

2
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118.bringup
import chisel3._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._

2
generators/boom

Submodule generators/boom updated: 051dbadb6d...1b1f210bcf

2
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import freechips.rocketchip.config.{Parameters, Field}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{ResetCatchAndSync}
import chipyard.iobinders._

19
generators/chipyard/src/main/scala/ConfigFinder.scala Normal file
View File

@@ -0,0 +1,19 @@
package chipyard
import org.reflections.Reflections
import org.reflections.scanners.Scanners.SubTypes
import scala.jdk.CollectionConverters._
import scala.collection.{SortedSet}
import org.chipsalliance.cde.config.{Config}
object ConfigFinder {
def main(args: Array[String]) = {
val reflections = new Reflections()
val classes = reflections.get(SubTypes.of(classOf[Config]).asClass()).asScala
val sortedClasses = SortedSet[String]() ++ classes.map(_.getName)
for (cls <- sortedClasses) {
println(cls)
}
}
}

2
generators/chipyard/src/main/scala/Cospike.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.experimental.{IntParam, StringParam, IO}
import chisel3.util._
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------

8
generators/chipyard/src/main/scala/HarnessBinders.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.devices.debug._
@@ -22,8 +22,8 @@ import barstools.iocell.chisel._
import testchipip._
import chipyard._
import chipyard.clocking.{HasChipyardPRCI}
import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, ClockWithFreq}
import chipyard.clocking.{HasChipyardPRCI, ClockWithFreq}
import chipyard.iobinders.{GetSystemParameters, JTAGChipIO}
import tracegen.{TraceGenSystemModuleImp}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
@@ -154,7 +154,7 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
ports.map({ port =>
// DOC include start: HarnessClockInstantiatorEx
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).requestClockBundle("mem_over_serial_tl_clock", memFreq)
val memOverSerialTLClockBundle = th.harnessClockInstantiator.requestClockBundle("mem_over_serial_tl_clock", memFreq)
val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
system.serdesser.get,

96
generators/chipyard/src/main/scala/HarnessClocks.scala Normal file
View File

@@ -0,0 +1,96 @@
package chipyard
import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import freechips.rocketchip.diplomacy.{LazyModule}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.util.{ResetCatchAndSync}
import freechips.rocketchip.prci._
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
import chipyard.iobinders.HasIOBinders
import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
import chipyard.HarnessClockInstantiatorKey
// HarnessClockInstantiators are classes which generate clocks that drive
// TestHarness simulation models and any Clock inputs to the ChipTop
trait HarnessClockInstantiator {
val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty
// request a clock bundle at a particular frequency
def requestClockBundle(name: String, freqRequested: Double): ClockBundle = {
val clockBundle = Wire(new ClockBundle(ClockBundleParameters()))
_clockMap(name) = (freqRequested, clockBundle)
clockBundle
}
// refClock is the clock generated by TestDriver that is
// passed to the TestHarness as its implicit clock
def instantiateHarnessClocks(refClock: ClockBundle): Unit
}
// The DividerOnlyHarnessClockInstantiator uses synthesizable clock divisors
// to approximate frequency ratios between the requested clocks
class DividerOnlyHarnessClockInstantiator extends HarnessClockInstantiator {
// connect all clock wires specified to a divider only PLL
def instantiateHarnessClocks(refClock: ClockBundle): Unit = {
val sinks = _clockMap.map({ case (name, (freq, bundle)) =>
ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name))
}).toSeq
val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks)
pllConfig.emitSummaries()
val dividedClocks = LinkedHashMap[Int, Clock]()
def instantiateDivider(div: Int): Clock = {
val divider = Module(new ClockDividerN(div))
divider.suggestName(s"ClockDivideBy${div}")
divider.io.clk_in := refClock.clock
dividedClocks(div) = divider.io.clk_out
divider.io.clk_out
}
// connect wires to clock source
for (sinkParams <- sinks) {
// bypass the reference freq. (don't create a divider + reset sync)
val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) {
val div = pllConfig.sinkDividerMap(sinkParams)
val divClock = dividedClocks.getOrElse(div, instantiateDivider(div))
(divClock, ResetCatchAndSync(divClock, refClock.reset.asBool))
} else {
(refClock.clock, refClock.reset)
}
_clockMap(sinkParams.name.get)._2.clock := divClock
_clockMap(sinkParams.name.get)._2.reset := divReset
}
}
}
// The AbsoluteFreqHarnessClockInstantiator uses a Verilog blackbox to
// provide the precise requested frequency.
// This ClockInstantiator cannot be synthesized, run in Verilator, or run in FireSim
// It is useful for VCS/Xcelium-driven RTL simulations
class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator {
def instantiateHarnessClocks(refClock: ClockBundle): Unit = {
val sinks = _clockMap.map({ case (name, (freq, bundle)) =>
ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name))
}).toSeq
// connect wires to clock source
for (sinkParams <- sinks) {
val source = Module(new ClockSourceAtFreq(sinkParams.take.get.freqMHz))
source.io.power := true.B
source.io.gate := false.B
_clockMap(sinkParams.name.get)._2.clock := source.io.clk
_clockMap(sinkParams.name.get)._2.reset := refClock.reset
}
}
}
class WithAbsoluteFreqHarnessClockInstantiator extends Config((site, here, up) => {
case HarnessClockInstantiatorKey => () => new AbsoluteFreqHarnessClockInstantiator
})

45
generators/chipyard/src/main/scala/IOBinders.scala
View File

@@ -3,7 +3,7 @@ package chipyard.iobinders
import chisel3._
import chisel3.experimental.{Analog, IO, DataMirror}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
@@ -248,7 +248,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => {
InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
system.debug.map({ debug =>
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
@@ -425,45 +425,4 @@ class WithDontTouchPorts extends OverrideIOBinder({
(system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
})
class ClockWithFreq(val freqMHz: Double) extends Bundle {
val clock = Clock()
}
class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
system.connectImplicitClockSinkNode(implicitClockSinkNode)
InModuleBody {
val implicit_clock = implicitClockSinkNode.in.head._1.clock
val implicit_reset = implicitClockSinkNode.in.head._1.reset
system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
l.clock := implicit_clock
l.reset := implicit_reset
}}
}
// Connect all other requested clocks
val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val dividerOnlyClockGen = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator"))
(system.allClockGroupsNode
:= dividerOnlyClockGen.node
:= referenceClockSource)
InModuleBody {
val clock_wire = Wire(Input(new ClockWithFreq(dividerOnlyClockGen.module.referenceFreq)))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
referenceClockSource.out.unzip._1.map { o =>
o.clock := clock_wire.clock
o.reset := reset_wire
}
(Seq(clock_io, reset_io), clockIOCell ++ resetIOCell)
}
}
})

2
generators/chipyard/src/main/scala/SpikeTile.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{IntParam, StringParam, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._

6
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -9,9 +9,9 @@ import chisel3._
import chisel3.internal.sourceinfo.{SourceInfo}
import freechips.rocketchip.prci._
import freechips.rocketchip.config.{Field, Parameters}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey}
import sifive.blocks.devices.uart.{HasPeripheryUART, PeripheryUARTKey}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
@@ -65,12 +65,14 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
t.uarts.foreach(u => Resource(chosen, "uart").bind(ResourceAlias(u.device.label)))
}
}
case _ =>
}
}
}
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
with HasTiles
with HasPeripheryDebug
with CanHaveHTIF
with CanHaveChosenInDTS
{

10
generators/chipyard/src/main/scala/System.scala
View File

@@ -7,7 +7,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Parameters, Field}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
@@ -31,6 +31,14 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
// If there is no bootrom, the tile reset vector bundle will be tied to zero
if (bootROM.isEmpty) {
val fakeResetVectorSourceNode = BundleBridgeSource[UInt]()
InModuleBody { fakeResetVectorSourceNode.bundle := 0.U }
tileResetVectorNexusNode := fakeResetVectorSourceNode
}
override lazy val module = new ChipyardSystemModule(this)
}

55
generators/chipyard/src/main/scala/TestHarness.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
@@ -18,9 +18,11 @@ import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p))
case object DefaultClockFrequencyKey extends Field[Double](100.0) // MHz
case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator](() => new DividerOnlyHarnessClockInstantiator)
trait HasHarnessSignalReferences {
implicit val p: Parameters
val harnessClockInstantiator = p(HarnessClockInstantiatorKey)()
// clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset)
var refClockFreq: Double = p(DefaultClockFrequencyKey)
def setRefClockFreq(freqMHz: Double) = { refClockFreq = freqMHz }
@@ -30,53 +32,6 @@ trait HasHarnessSignalReferences {
def success: Bool
}
class HarnessClockInstantiator {
private val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty
// request a clock bundle at a particular frequency
def requestClockBundle(name: String, freqRequested: Double): ClockBundle = {
val clockBundle = Wire(new ClockBundle(ClockBundleParameters()))
_clockMap(name) = (freqRequested, clockBundle)
clockBundle
}
// connect all clock wires specified to a divider only PLL
def instantiateHarnessDividerPLL(refClock: ClockBundle): Unit = {
val sinks = _clockMap.map({ case (name, (freq, bundle)) =>
ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name))
}).toSeq
val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks)
pllConfig.emitSummaries()
val dividedClocks = LinkedHashMap[Int, Clock]()
def instantiateDivider(div: Int): Clock = {
val divider = Module(new ClockDividerN(div))
divider.suggestName(s"ClockDivideBy${div}")
divider.io.clk_in := refClock.clock
dividedClocks(div) = divider.io.clk_out
divider.io.clk_out
}
// connect wires to clock source
for (sinkParams <- sinks) {
// bypass the reference freq. (don't create a divider + reset sync)
val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) {
val div = pllConfig.sinkDividerMap(sinkParams)
val divClock = dividedClocks.getOrElse(div, instantiateDivider(div))
(divClock, ResetCatchAndSync(divClock, refClock.reset.asBool))
} else {
(refClock.clock, refClock.reset)
}
_clockMap(sinkParams.name.get)._2.clock := divClock
_clockMap(sinkParams.name.get)._2.reset := divReset
}
}
}
case object HarnessClockInstantiatorKey extends Field[HarnessClockInstantiator](new HarnessClockInstantiator)
class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSignalReferences {
val io = IO(new Bundle {
val success = Output(Bool())
@@ -96,7 +51,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
val refClkBundle = p(HarnessClockInstantiatorKey).requestClockBundle("buildtop_reference_clock", getRefClockFreq * (1000 * 1000))
val refClkBundle = harnessClockInstantiator.requestClockBundle("buildtop_reference_clock", getRefClockFreq * (1000 * 1000))
buildtopClock := refClkBundle.clock
buildtopReset := WireInit(refClkBundle.reset)
@@ -104,5 +59,5 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
implicitHarnessClockBundle.clock := clock
implicitHarnessClockBundle.reset := reset
p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle)
harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
}

2
generators/chipyard/src/main/scala/TestSuites.scala
View File

@@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{XLen, TileParams}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
/**

127
generators/chipyard/src/main/scala/clocking/ClockBinders.scala Normal file
View File

@@ -0,0 +1,127 @@
package chipyard.clocking
import chisel3._
import chisel3.util._
import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey}
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import barstools.iocell.chisel._
class ClockWithFreq(val freqMHz: Double) extends Bundle {
val clock = Clock()
}
// This uses synthesizable clock divisors to approximate frequency rations
// between the requested clocks. This is currently the defualt clock generator "model",
// as it can be used in VCS/Xcelium/Verilator/FireSim
class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
system.connectImplicitClockSinkNode(implicitClockSinkNode)
InModuleBody {
val implicit_clock = implicitClockSinkNode.in.head._1.clock
val implicit_reset = implicitClockSinkNode.in.head._1.reset
system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
l.clock := implicit_clock
l.reset := implicit_reset
}}
}
// Connect all other requested clocks
val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val dividerOnlyClockGen = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator"))
(system.allClockGroupsNode
:= dividerOnlyClockGen.node
:= referenceClockSource)
InModuleBody {
val clock_wire = Wire(Input(new ClockWithFreq(dividerOnlyClockGen.module.referenceFreq)))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
referenceClockSource.out.unzip._1.map { o =>
o.clock := clock_wire.clock
o.reset := reset_wire
}
(Seq(clock_io, reset_io), clockIOCell ++ resetIOCell)
}
}
})
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with verilator or firesim
class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
system.connectImplicitClockSinkNode(implicitClockSinkNode)
InModuleBody {
val implicit_clock = implicitClockSinkNode.in.head._1.clock
val implicit_reset = implicitClockSinkNode.in.head._1.reset
system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
l.clock := implicit_clock
l.reset := implicit_reset
}}
}
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource
val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
pllCtrlSink := pllCtrl.ctrlNode
InModuleBody {
val clock_wire = Wire(Input(new ClockWithFreq(80)))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
o.clock := clock_wire.clock
o.reset := reset_wire
}
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
fake_pll.io.power := pllCtrlSink.in(0)._1.power
fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
pllClockSource.out.unzip._1.map { o =>
o.clock := fake_pll.io.clk
o.reset := reset_wire
}
(Seq(clock_io, reset_io), clockIOCell ++ resetIOCell)
}
}
})

2
generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
View File

@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import freechips.rocketchip.config.{Parameters, Config, Field}
import org.chipsalliance.cde.config.{Parameters, Config, Field}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
View File

@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts

36
generators/chipyard/src/main/scala/clocking/FakePLL.scala Normal file
View File

@@ -0,0 +1,36 @@
package chipyard.clocking
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.util._
class FakePLLCtrlBundle extends Bundle {
val gate = Bool()
val power = Bool()
}
class FakePLLCtrl(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
val device = new SimpleDevice(s"pll", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val ctrlNode = BundleBridgeSource(() => Output(new FakePLLCtrlBundle))
lazy val module = new LazyModuleImp(this) {
// This PLL only has 2 address, the gate and power
// Both should be set to turn on the PLL
// TODO: Should these be reset by the top level reset pin?
val gate_reg = Module(new AsyncResetRegVec(w=1, init=0))
val power_reg = Module(new AsyncResetRegVec(w=1, init=0))
ctrlNode.out(0)._1.gate := gate_reg.io.q
ctrlNode.out(0)._1.power := power_reg.io.q
tlNode.regmap(
0 -> Seq(RegField.rwReg(1, gate_reg.io)),
4 -> Seq(RegField.rwReg(1, power_reg.io))
)
}
}

16
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
@@ -20,7 +20,8 @@ import chipyard.{DefaultClockFrequencyKey}
case class ChipyardPRCIControlParams(
slaveWhere: TLBusWrapperLocation = CBUS,
baseAddress: BigInt = 0x100000,
enableTileClockGating: Boolean = true
enableTileClockGating: Boolean = true,
enableTileResetSetting: Boolean = true
)
@@ -72,12 +73,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
val clockGroupCombiner = ClockGroupCombiner()
val resetSynchronizer = ClockGroupResetSynchronizer()
val tileClockGater = prci_ctrl_domain {
TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating)
}
val tileResetSetter = prci_ctrl_domain {
val tileClockGater = if (prciParams.enableTileClockGating) { prci_ctrl_domain {
TileClockGater(prciParams.baseAddress + 0x00000, tlbus)
} } else { ClockGroupEphemeralNode() }
val tileResetSetter = if (prciParams.enableTileResetSetting) { prci_ctrl_domain {
TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)
}
} } else { ClockGroupEphemeralNode() }
(aggregator
:= frequencySpecifier
:= clockGroupCombiner

56
generators/chipyard/src/main/scala/clocking/TLClockDivider.scala Normal file
View File

@@ -0,0 +1,56 @@
package chipyard.clocking
import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
import testchipip._
// This module adds a TileLink memory-mapped clock divider to the clock graph
// The output clock/reset pairs from this module should be synchronized later
class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice(s"clk-div-ctrl", Nil)
val clockNode = ClockGroupIdentityNode()
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
lazy val module = new LazyModuleImp(this) {
require (clockNode.out.size == 1)
val sources = clockNode.in.head._1.member.data.toSeq
val sinks = clockNode.out.head._1.member.elements.toSeq
require (sources.size == sinks.size)
val nSinks = sinks.size
val regs = (0 until nSinks) .map { i =>
val sinkName = sinks(i)._1
val asyncReset = sources(i).reset
val reg = withReset (asyncReset) {
Module(new AsyncResetRegVec(w=divBits, init=0))
}
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
sinks(i)._2.clock := withClockAndReset(sources(i).clock, asyncReset) {
val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
divider.io.divisor := reg.io.q
divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
divider.io.clockOut
}
// Note this is not synchronized to the output clock, which takes time to appear
// so this is still asyncreset
// Stretch the reset for 40 cycles, to give enough time to reset any downstream
// digital logic
sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
reg
}
tlNode.regmap((0 until nSinks).map { i =>
i * 4 -> Seq(RegField.rwReg(divBits, regs(i).io))
}: _*)
}
}

73
generators/chipyard/src/main/scala/clocking/TLClockSelector.scala Normal file
View File

@@ -0,0 +1,73 @@
package chipyard.clocking
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
import testchipip._
object ResetStretcher {
def apply(clock: Clock, reset: Reset, cycles: Int): Reset = {
withClockAndReset(clock, reset) {
val n = log2Ceil(cycles)
val count = Module(new AsyncResetRegVec(w=n, init=0))
val resetout = Module(new AsyncResetRegVec(w=1, init=1))
count.io.en := resetout.io.q
count.io.d := count.io.q + 1.U
resetout.io.en := resetout.io.q
resetout.io.d := count.io.q < (cycles-1).U
resetout.io.q.asBool
}
}
}
case class ClockSelNode()(implicit valName: ValName)
extends MixedNexusNode(ClockImp, ClockGroupImp)(
dFn = { d => ClockGroupSourceParameters() },
uFn = { u => ClockSinkParameters() }
)
// This module adds a TileLink memory-mapped clock mux for each downstream clock domain
// in the clock graph. The output clock/reset should be synchronized downstream
class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("clk-sel-ctrl", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val clockNode = ClockSelNode()
lazy val module = new LazyModuleImp(this) {
val asyncReset = clockNode.in.map(_._1).map(_.reset).toSeq(0)
val clocks = clockNode.in.map(_._1).map(_.clock)
val (outClocks, _) = clockNode.out.head
val (sinkNames, sinks) = outClocks.member.elements.toSeq.unzip
val regs = (0 until sinks.size).map { i =>
val sinkName = sinkNames(i)
val sel = Wire(UInt(log2Ceil(clocks.size).W))
val reg = withReset(asyncReset) { Module(new AsyncResetRegVec(w=log2Ceil(clocks.size), init=0)) }
sel := reg.io.q
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux")
val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
mux.io.sel := sel
mux.io.resetAsync := asyncReset.asAsyncReset
sinks(i).clock := mux.io.clockOut
// Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
reg
}
tlNode.regmap((0 until sinks.size).map { i =>
i * 4 -> Seq(RegField.rwReg(log2Ceil(clocks.size), regs(i).io))
}: _*)
}
}

12
generators/chipyard/src/main/scala/clocking/TileClockGater.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
@@ -19,7 +19,7 @@ import freechips.rocketchip.subsystem._
* flag will generate the registers, preserving the same memory map and behavior, but will not
* generate any gaters
*/
class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule
class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, valName: ValName) extends LazyModule
{
val device = new SimpleDevice(s"clock-gater", Nil)
val clockNode = ClockGroupIdentityNode()
@@ -31,8 +31,8 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit
val regs = (0 until nSinks).map({i =>
val sinkName = sinks(i)._1
val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) }
if (sinkName.contains("tile") && enable) {
println(s"ClockGate for ${sinkName} regmapped at ${(address+i*4).toString(16)}")
if (sinkName.contains("tile")) {
println(s"${(address+i*4).toString(16)}: Tile $sinkName clock gate")
sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool)
sinks(i)._2.reset := sources(i).reset
} else {
@@ -47,8 +47,8 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit
}
object TileClockGater {
def apply(address: BigInt, tlbus: TLBusWrapper, enable: Boolean)(implicit p: Parameters, v: ValName) = {
val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes, enable))
def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = {
val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes))
tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() }
gater.clockNode
}

8
generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
@@ -39,16 +39,16 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
}): _*)
val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>
n -> (tile_async_resets(i), r_tile_resets(i).io.q)
n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4)
})
(clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) =>
(o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) =>
oD.clock := iD.clock
oD.reset := iD.reset
for ((n, (rIn, rOut)) <- tileMap) {
for ((n, (rIn, rOut, addr)) <- tileMap) {
if (name.contains(n)) {
println(name, n)
println(s"${addr.toString(16)}: Tile $name reset control")
// Async because the reset coming out of the AsyncResetRegVec is
// clocked to the bus this is attached to, not the clock in this
// clock bundle. We expect a ClockGroupResetSynchronizer downstream

8
generators/chipyard/src/main/scala/config/AbstractConfig.scala
View File

@@ -1,6 +1,6 @@
package chipyard.config
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// --------------
// Chipyard abstract ("base") configuration
@@ -40,7 +40,11 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithExtInterruptIOCells ++
new chipyard.iobinders.WithCustomBootPin ++
new chipyard.iobinders.WithDividerOnlyClockGenerator ++
// Default behavior is to use a divider-only clock-generator
// This works in VCS, Verilator, and FireSim/
// This should get replaced with a PLL-like config instead
new chipyard.clocking.WithDividerOnlyClockGenerator ++
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM

2
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// BOOM Configs

2
generators/chipyard/src/main/scala/config/CVA6Configs.scala
View File

@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// CVA6 Configs

44
generators/chipyard/src/main/scala/config/ChipConfigs.scala Normal file
View File

@@ -0,0 +1,44 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._
// A simple config demonstrating how to set up a basic chip in Chipyard
class ChipLikeQuadRocketConfig extends Config(
//==================================
// Set up TestHarness
//==================================
new chipyard.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
// NOTE: This only simulates properly in VCS
//==================================
// Set up tiles
//==================================
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
//==================================
// Set up I/O
//==================================
new testchipip.WithSerialTLWidth(4) ++
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness
new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
//==================================
// Set up clock./reset
//==================================
new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure
// Create two clock groups, uncore and fbus, in addition to the tile clock groups
new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus") ++
new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++
// Set up the crossings
new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new chipyard.config.AbstractConfig)

2
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// Heterogenous Configs

2
generators/chipyard/src/main/scala/config/IbexConfigs.scala
View File

@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// Ibex Configs

2
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------

2
generators/chipyard/src/main/scala/config/NoCConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{SBUS, MBUS}

2
generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// A empty config with no cores. Useful for testing
class NoCoresConfig extends Config(

2
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ---------------------------------------------------------

2
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------

4
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// --------------
@@ -93,6 +93,7 @@ class MbusScratchpadRocketConfig extends Config(
// DOC include end: mbusscratchpadrocket
class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
// Frequency specifications
new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540
@@ -103,7 +104,6 @@ class MulticlockRocketConfig extends Config(
// Crossing specifications
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new chipyard.config.AbstractConfig)

2
generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// --------------

2
generators/chipyard/src/main/scala/config/SodorConfigs.scala
View File

@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
class Sodor1StageConfig extends Config(
// Create a Sodor 1-stage core

3
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
View File

@@ -1,7 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.rocket.{DCacheParams}
import org.chipsalliance.cde.config.{Config}
// Configs which instantiate a Spike-simulated
// tile that interacts with the Chipyard SoC

4
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.rocket.{DCacheParams}
class AbstractTraceGenConfig extends Config(
@@ -9,7 +9,7 @@ class AbstractTraceGenConfig extends Config(
new chipyard.harness.WithClockAndResetFromHarness ++
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
new chipyard.iobinders.WithDividerOnlyClockGenerator ++
new chipyard.clocking.WithDividerOnlyClockGenerator ++
new chipyard.config.WithTracegenSystem ++
new chipyard.config.WithNoSubsystemDrivenClocks ++
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++

2
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import constellation.channel._
import constellation.routing._
import constellation.topology._

2
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
View File

@@ -4,7 +4,7 @@ import scala.util.matching.Regex
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Field, Parameters, Config}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._

2
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -4,7 +4,7 @@ import scala.util.matching.Regex
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
import freechips.rocketchip.stage.phases.TargetDirKey

2
generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
View File

@@ -2,7 +2,7 @@ package chipyard.config
import chisel3._
import freechips.rocketchip.config.{Field, Parameters, Config}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy._

2
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
View File

@@ -1,6 +1,6 @@
package chipyard.config
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
import freechips.rocketchip.diplomacy.{DTSTimebase}

2
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -2,7 +2,7 @@ package chipyard.config
import chisel3._
import freechips.rocketchip.config.{Field, Parameters, Config}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}

2
generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
View File

@@ -1,6 +1,6 @@
package chipyard.config
import freechips.rocketchip.config.{Config, Field, Parameters}
import org.chipsalliance.cde.config.{Config, Field, Parameters}
import tracegen.{TraceGenSystem}
import chipyard.{BuildSystem}
import chipyard.clocking.{HasChipyardPRCI}

2
generators/chipyard/src/main/scala/example/CustomChipTop.scala
View File

@@ -3,7 +3,7 @@ package chipyard.example
import chisel3._
import chipyard.iobinders._
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy.{InModuleBody}
import barstools.iocell.chisel._
import chipyard._

145
generators/chipyard/src/main/scala/example/FlatChipTop.scala Normal file
View File

@@ -0,0 +1,145 @@
package chipyard.example
import chisel3._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
import freechips.rocketchip.tilelink.{TLBuffer}
import chipyard.{BuildSystem, DigitalTop}
import chipyard.clocking._
import chipyard.iobinders.{IOCellKey, JTAGChipIO}
import barstools.iocell.chisel._
// This "FlatChipTop" uses no IOBinders, so all the IO have
// to be explicitly constructed.
// This only supports the base "DigitalTop"
class FlatChipTop(implicit p: Parameters) extends LazyModule {
override lazy val desiredName = "ChipTop"
val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop]
//========================
// Diplomatic clock stuff
//========================
val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
system.connectImplicitClockSinkNode(implicitClockSinkNode)
val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource
val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
pllCtrlSink := pllCtrl.ctrlNode
val debugClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters()))
debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode
def debugClockBundle = debugClockSinkNode.in.head._1
override lazy val module = new FlatChipTopImpl
class FlatChipTopImpl extends LazyRawModuleImp(this) {
//=========================
// Clock/reset
//=========================
val implicit_clock = implicitClockSinkNode.in.head._1.clock
val implicit_reset = implicitClockSinkNode.in.head._1.reset
system.module match { case l: LazyModuleImp => {
l.clock := implicit_clock
l.reset := implicit_reset
}}
val clock_wire = Wire(Input(new ClockWithFreq(80)))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_pad, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
o.clock := clock_wire.clock
o.reset := reset_wire
}
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
fake_pll.io.power := pllCtrlSink.in(0)._1.power
fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
pllClockSource.out.unzip._1.map { o =>
o.clock := fake_pll.io.clk
o.reset := reset_wire
}
//=========================
// Custom Boot
//=========================
val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey))
//=========================
// Serialized TileLink
//=========================
val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
//=========================
// JTAG/Debug
//=========================
val debug = system.debug.get
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } }
// Tie off extTrigger
debug.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
// Tie off disableDebug
debug.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
debug.systemjtag.map { j =>
j.reset := ResetCatchAndSync(j.jtag.TCK, debugClockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
Debug.connectDebugClockAndReset(Some(debug), debugClockBundle.clock)
// Add IOCells for the DMI/JTAG/APB ports
require(!debug.clockeddmi.isDefined)
require(!debug.apb.isDefined)
val (jtag_pad, jtagIOCells) = debug.systemjtag.map { j =>
val jtag_wire = Wire(new JTAGChipIO)
j.jtag.TCK := jtag_wire.TCK
j.jtag.TMS := jtag_wire.TMS
j.jtag.TDI := jtag_wire.TDI
jtag_wire.TDO := j.jtag.TDO.data
IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
}.get
//==========================
// UART
//==========================
require(system.uarts.size == 1)
val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
}
}

83
generators/chipyard/src/main/scala/example/FlatTestHarness.scala Normal file
View File

@@ -0,0 +1,83 @@
package chipyard.example
import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{PlusArg}
import freechips.rocketchip.subsystem.{CacheBlockBytes}
import freechips.rocketchip.devices.debug.{SimJTAG}
import freechips.rocketchip.jtag.{JTAGIO}
import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM}
import chipyard.{BuildTop}
// A "flat" TestHarness that doesn't use IOBinders
// use with caution.
// This example is hard-coded to work only for FlatChipTop, and the ChipLikeRocketConfig
class FlatTestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val success = Output(Bool())
})
// This only works with FlatChipTop
val lazyDut = LazyModule(new FlatChipTop).suggestName("chiptop")
val dut = Module(lazyDut.module)
// Clock
val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz"))
clock_source.io.power := true.B
clock_source.io.gate := false.B
dut.clock_pad.clock := clock_source.io.clk
// Reset
dut.reset_pad := reset.asAsyncReset
// Custom boot
dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1)
// Serialized TL
val sVal = p(SerialTLKey).get
require(sVal.axiMemOverSerialTLParams.isDefined)
require(sVal.isMemoryDevice)
val axiDomainParams = sVal.axiMemOverSerialTLParams.get
val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
withClockAndReset(clock, reset) {
val memOverSerialTLClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
memOverSerialTLClockBundle.clock := clock
memOverSerialTLClockBundle.reset := reset
val serial_bits = SerialAdapter.asyncQueue(dut.serial_tl_pad, clock, reset)
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
lazyDut.system.serdesser.get,
serial_bits,
memOverSerialTLClockBundle,
reset)
io.success := SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, clock, reset)
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
val memSize = sVal.memParams.size
val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits
mem.io.clock := axi_port.clock
mem.io.reset := axi_port.reset
}
}
// JTAG
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := dut.jtag_pad.TDO
jtag_wire.TDO.driven := true.B
dut.jtag_pad.TCK := jtag_wire.TCK
dut.jtag_pad.TMS := jtag_wire.TMS
dut.jtag_pad.TDI := jtag_wire.TDI
val dtm_success = WireInit(false.B)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, clock, reset.asBool, ~(reset.asBool), dtm_success)
// UART
UARTAdapter.connect(Seq(dut.uart_pad))
}

2
generators/chipyard/src/main/scala/example/GCD.scala
View File

@@ -5,7 +5,7 @@ import chisel3.util._
import chisel3.experimental.{IntParam, BaseModule}
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/InitZero.scala
View File

@@ -3,7 +3,7 @@ package chipyard.example
import chisel3._
import chisel3.util._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/NodeTypes.scala
View File

@@ -1,6 +1,6 @@
package chipyard.example
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
View File

@@ -2,7 +2,7 @@
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink.TLRegisterNode

2
generators/chipyard/src/main/scala/example/TutorialTile.scala
View File

@@ -3,7 +3,7 @@ package chipyard.example
import chisel3._
import chisel3.util._
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._

2
generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
View File

@@ -5,7 +5,7 @@ import chisel3.util._
import dspblocks._
import dsptools.numbers._
import freechips.rocketchip.amba.axi4stream._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
View File

@@ -8,7 +8,7 @@ import chisel3.util._
import dspblocks._
import dsptools.numbers._
import freechips.rocketchip.amba.axi4stream._
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
View File

@@ -8,7 +8,7 @@ import chisel3.util._
import dspblocks._
import dsptools.numbers._
import freechips.rocketchip.amba.axi4stream._
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
View File

@@ -6,7 +6,7 @@ package chipyard.stage.phases
import scala.util.Try
import scala.collection.mutable
import chipsalliance.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import chisel3.stage.phases.Elaborate
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}

2
generators/chipyard/src/main/scala/unittest/TestHarness.scala
View File

@@ -1,7 +1,7 @@
package chipyard.unittest
import chisel3._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
class TestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle { val success = Output(Bool()) })

2
generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
View File

@@ -1,6 +1,6 @@
package chipyard.unittest
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}
class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {

2
generators/constellation

Submodule generators/constellation updated: 4606ee19b7...e9f1c828ca

2
generators/cva6

Submodule generators/cva6 updated: 737fd83b82...0011494bb7

2
generators/fft-generator

Submodule generators/fft-generator updated: a31bd038dd...be8ab768bd

4
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -6,9 +6,9 @@ import chisel3._
import chisel3.experimental.annotate
import chisel3.util.experimental.BoringUtils
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{RocketTile}

2
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -9,7 +9,7 @@ import chisel3.experimental.{IO}
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}

2
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -4,7 +4,7 @@ import java.io.File
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Parameters, Config}
import org.chipsalliance.cde.config.{Parameters, Config}
import freechips.rocketchip.groundtest.TraceGenParams
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._

2
generators/gemmini

Submodule generators/gemmini updated: 4dd19f3e93...965ea0b3c5

2
generators/hwacha

Submodule generators/hwacha updated: e1be8e2a41...d01ca1e7f8

2
generators/ibex

Submodule generators/ibex updated: 626127f229...916fb7a6ff

2
generators/icenet

Submodule generators/icenet updated: 90d52a6a84...ce1ec55c1f

2
generators/mempress

Submodule generators/mempress updated: b9eaedc061...295ae0854a

2
generators/nvdla

Submodule generators/nvdla updated: 2b17011b26...7130a5c0f7

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: d6ccc5de5c...c051956d3b

2
generators/rocket-chip

Submodule generators/rocket-chip updated: ed63528931...cbe252aff1

2
generators/sha3

Submodule generators/sha3 updated: 8c5d244303...1fa5ef8ae5

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