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split verilator compilation into phases

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This commit is contained in:
Howard Mao
2016-10-27 16:57:00 -07:00
parent d87c8159a0
commit d22f0cab68
1 changed files with 15 additions and 6 deletions
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21
verisim/Makefile
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@@ -7,8 +7,8 @@ CONFIG ?= DefaultExampleConfig
CFG_PROJECT ?= $(PROJECT)
TB ?= TestDriver
sim = simulator-$(PROJECT)-$(CONFIG)
sim_debug = simulator-$(PROJECT)-$(CONFIG)-debug
sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
default: $(sim)
@@ -36,17 +36,26 @@ model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(MODEL).h
model_header_debug = $(model_dir_debug)/V$(MODEL).h
$(sim): $(sim_vsrcs) $(sim_csrcs) $(INSTALLED_VERILATOR)
model_mk = $(model_dir)/V$(MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
$(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim_dir)/$@ $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header)"
touch $@
$(sim): $(model_mk) $(sim_csrcs)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
$(sim_debug): $(sim_vsrcs) $(sim_csrcs) $(INSTALLED_VERILATOR)
$(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_dir)/$@ $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-o $(sim_debug) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header_debug)"
touch $@
$(sim_debug): $(model_mk_debug) $(sim_csrcs)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk