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Add WithCoalescer to RadianceROMConfig

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This commit is contained in:
Hansung Kim
2023-10-25 20:06:44 -07:00
parent 30a136ee27
commit d6624f0741
1 changed files with 10 additions and 7 deletions
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17
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -37,13 +37,16 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
class RadianceROMConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig)
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig)
class RadianceConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++