wu-arch/chipyard
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Merge remote-tracking branch 'origin/main' into conda

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This commit is contained in:
Abraham Gonzalez
2022-09-01 18:50:36 +00:00
parent 54423cca01 8a96f7c177
commit d7990e5639
4 changed files with 8 additions and 8 deletions
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2
.github/scripts/check-commit.sh vendored
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@@ -105,7 +105,7 @@ search
submodules=("fpga-shells") submodules=("fpga-shells")
dir="fpga" dir="fpga"
branches=("master") branches=("main")
search search
# turn off verbose printing to make this easier to read # turn off verbose printing to make this easier to read

6
.gitmodules vendored
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@@ -15,7 +15,7 @@
url = https://github.com/riscv-boom/riscv-boom.git url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"] [submodule "generators/sifive-blocks"]
path = generators/sifive-blocks path = generators/sifive-blocks
url = https://github.com/sifive/sifive-blocks.git url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"] [submodule "generators/hwacha"]
path = generators/hwacha path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git url = https://github.com/ucb-bar/hwacha.git
@@ -27,7 +27,7 @@
url = https://github.com/firesim/icenet.git url = https://github.com/firesim/icenet.git
[submodule "generators/block-inclusivecache-sifive"] [submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache path = generators/sifive-cache
url = https://github.com/sifive/block-inclusivecache-sifive.git url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "vlsi/hammer"] [submodule "vlsi/hammer"]
path = vlsi/hammer path = vlsi/hammer
url = https://github.com/ucb-bar/hammer.git url = https://github.com/ucb-bar/hammer.git
@@ -84,7 +84,7 @@
url = https://github.com/ucb-bar/riscv-sodor.git url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"] [submodule "fpga/fpga-shells"]
path = fpga/fpga-shells path = fpga/fpga-shells
url = https://github.com/sifive/fpga-shells.git url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/api-config-chipsalliance"] [submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git url = https://github.com/chipsalliance/api-config-chipsalliance.git

6
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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@@ -38,17 +38,17 @@ class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockN
fMHz) fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get.toDouble / (1000 * 1000))
}) })
class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get.toDouble / (1000 * 1000))
}) })
class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => {
case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
Seq((cName: String) => site(key).dtsFrequency.flatMap { f => Seq((cName: String) => site(key).dtsFrequency.flatMap { f =>
re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } re.findFirstIn(cName).map {_ => (f.toDouble / (1000 * 1000)) }
}) })
}) })

2
generators/testchipip

Submodule generators/testchipip updated: 03535f56a6...eea390af19