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Merge pull request #1723 from tymcauley/resolve-chisel5-errors

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Update deprecated APIs to prepare for Chisel 5
This commit is contained in:
Jerry Zhao
2024-01-04 11:28:45 -08:00
committed by GitHub
parent e6d4fe8739 0a42dd1ca1
commit d9bc036cb6
5 changed files with 6 additions and 5 deletions
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2
generators/chipyard/src/main/scala/SpikeTile.scala
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@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import chisel3.util._
import chisel3.experimental.{IntParam, StringParam, IO}
import chisel3.experimental.{IntParam, StringParam}
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/clocking/TileClockGater.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._

3
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
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@@ -1,7 +1,8 @@
package chipyard.iobinders
import chisel3._
import chisel3.experimental.{Analog, IO, DataMirror}
import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._