Merge remote-tracking branch 'origin/dev' into bump-gemmini

This commit is contained in:
Hasan Genc
2021-06-10 11:58:47 -07:00
16 changed files with 34 additions and 14 deletions

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@@ -90,7 +90,7 @@ else
fi
search
submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "firrtl-interpreter" "torture" "treadle")
submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "firrtl-interpreter" "torture" "treadle")
dir="tools"
if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
then

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@@ -6,7 +6,7 @@ version: 2.1
parameters:
tools-cache-version:
type: string
default: "v9"
default: "v10"
# default execution env.s
executors:
@@ -287,6 +287,7 @@ jobs:
executor: main-env
steps:
- run-tests:
tools-version: "esp-tools"
group-key: "group-accels"
project-key: "chipyard-sha3"
chipyard-streaming-fir-run-tests:

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@@ -65,6 +65,9 @@ case $1 in
$LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
;;
chipyard-sha3)
export RISCV=$LOCAL_ESP_DIR
export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib
export PATH=$RISCV/bin:$PATH
(cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
$LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv
;;

6
.gitmodules vendored
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@@ -134,3 +134,9 @@
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/sifive/fpga-shells.git
[submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git
[submodule "tools/rocket-dsp-utils"]
path = tools/rocket-dsp-utils
url = https://github.com/ucb-bar/rocket-dsp-utils

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@@ -185,7 +185,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
.sourceDependency(testchipip, testchipipLib)
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsptools`,
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -278,8 +278,16 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
"org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
))
lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket"))
.dependsOn(rocketchip, dsptools)
lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance"))
.settings(
commonSettings,
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.0.+" % "test",
"org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
))
lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
.dependsOn(rocketchip, `api-config-chipsalliance`, dsptools)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

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@@ -8,7 +8,7 @@ index 3123c4b8..487fc428 100644
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+// sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsptools`,
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -223,11 +223,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))