Update fpga-flow to remove chisel6-incompatible APIs

fpga/src/main/scala/arty/IOBinders.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.arty
 
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 

fpga/src/main/scala/vc707/TestHarness.scala

@@ -1,6 +1,5 @@
 package chipyard.fpga.vc707
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.vcu118
 
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}