changing tutorial VLSI_TOP to RocketTile to save time

.github/workflows/chipyard-full-flow.yml

@@ -123,29 +123,39 @@ jobs:
           # installs for example-sky130.yml
           conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
           git clone https://github.com/rahulk29/sram22_sky130_macros.git
-          echo "" >> example-sky130.yml
-          echo "# tutorial configs" >> example-sky130.yml
-          echo "technology.sky130.sky130A: $PWD/.conda-sky130/share/pdk/sky130A" >> example-sky130.yml
-          echo "technology.sky130.sram22_sky130_macros: $PWD/sram22_sky130_macros" >> example-sky130.yml
 
           # installs for example-openroad.yml
           conda create -y --prefix ./.conda-yosys yosys=0.27_4_gb58664d44
           conda create -y --prefix ./.conda-openroad openroad=2.0_7070_g0264023b6
           conda create -y --prefix ./.conda-klayout klayout=0.28.5_98_g87e2def28
           conda create -y --prefix ./.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
-          echo "" >> example-openroad.yml
-          echo "# tutorial configs" >> example-openroad.yml
-          echo "synthesis.yosys.yosys_bin: $PWD/.conda-yosys/bin/yosys" >> example-openroad.yml
-          echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> example-openroad.yml
-          echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> example-openroad.yml
-          echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> example-openroad.yml
-          echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> example-openroad.yml
+
+          echo "# Tutorial configs" > tutorial.yml
+          echo "# pdk" > tutorial.yml
+          echo "technology.sky130.sky130A: $PWD/.conda-sky130/share/pdk/sky130A" >> tutorial.yml
+          echo "technology.sky130.sram22_sky130_macros: $PWD/sram22_sky130_macros" >> tutorial.yml
+          echo "" >> tutorial.yml
+          echo "# tools" >> tutorial.yml
+          echo "synthesis.yosys.yosys_bin: $PWD/.conda-yosys/bin/yosys" >> tutorial.yml
+          echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> tutorial.yml
+          echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml
+          echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
+          echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
+          echo "" >> tutorial.yml
+          echo "# RocketTile clock name is 'clock'" >> tutorial.yml
+          echo "vlsi.inputs.clocks: [" >> tutorial.yml
+          echo "  {name: clock, period: 30ns, uncertainty: 3ns}" >> tutorial.yml
+          echo "]" >> tutorial.yml
+          echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
+          echo "par.openroad.timing_driven: false" >> tutorial.yml
+          echo "par.openroad.write_reports: false" >> tutorial.yml
 
           conda config --remove channels litex-hub
-          conda config --remove channels defaults
+          conda config --remove channels defaultss
 
           export tutorial=sky130-openroad
-          # TODO: consider setting VLSI_TOP=RocketTile
+          export EXTRA_CONFS="example-designs/sky130-openroad-rockettile.yml tutorial.yml"
+          export VLSI_TOP=RocketTile
           make buildfile
           make syn
           make par

vlsi/example-designs/sky130-openroad-rockettile.yml

@@ -0,0 +1,60 @@
+# Override configurations in ../example-sky130.yml and example-designs
+
+# Specify clock signals
+# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+vlsi.inputs.clocks: [
+  {name: "clock", period: "30ns", uncertainty: "3ns"}
+]
+
+# Placement Constraints
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "RocketTile"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 3000
+    margins:
+      left: 10
+      right: 0
+      top: 10
+      bottom: 10
+
+  # Place SRAM memory instances
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 450
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 850
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90

vlsi/tutorial.mk

@@ -30,7 +30,10 @@ ifeq ($(tutorial),sky130-openroad)
     TOOLS_CONF        ?= example-openroad.yml
     TECH_CONF         ?= example-sky130.yml
     DESIGN_CONF       ?= example-designs/sky130-openroad.yml
-    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
+    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), \
+                            example-designs/sky130-rocket.yml, \
+                            $(if $(filter $(VLSI_TOP),RocketTile), \
+                                example-designs/sky130-openroad-rockettile.yml, ))
     INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
     VLSI_OBJ_DIR      ?= build-sky130-openroad
     # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.