Merge pull request #129 from kevindna/master
Add name to IOCell definition
This commit is contained in:
@@ -59,7 +59,19 @@ class DigitalInIOCellBundle extends Bundle {
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val ie = Input(Bool())
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val ie = Input(Bool())
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}
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}
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trait IOCell extends BaseModule
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trait IOCell extends BaseModule {
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var iocell_name: Option[String] = None
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/** Set IOCell name
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* @param s Proposed name for the IOCell
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*
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* @return An inherited IOCell with given the proposed name
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*/
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def suggestName(s: String): this.type = {
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iocell_name = Some(s)
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super.suggestName(s)
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}
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}
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trait AnalogIOCell extends IOCell {
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trait AnalogIOCell extends IOCell {
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val io: AnalogIOCellBundle
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val io: AnalogIOCellBundle
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@@ -159,7 +171,9 @@ object IOCell {
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DataMirror.directionOf(coreSignal) match {
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DataMirror.directionOf(coreSignal) match {
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case ActualDirection.Input => {
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case ActualDirection.Input => {
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val iocell = typeParams.input()
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val iocell = typeParams.input()
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name.foreach(n => iocell.suggestName(n))
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name.foreach(n => {
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iocell.suggestName(n)
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})
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coreSignal := castFromBool(iocell.io.i)
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coreSignal := castFromBool(iocell.io.i)
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iocell.io.ie := true.B
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iocell.io.ie := true.B
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iocell.io.pad := castToBool(padSignal)
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iocell.io.pad := castToBool(padSignal)
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@@ -167,7 +181,9 @@ object IOCell {
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}
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}
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case ActualDirection.Output => {
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case ActualDirection.Output => {
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val iocell = typeParams.output()
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val iocell = typeParams.output()
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name.foreach(n => iocell.suggestName(n))
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name.foreach(n => {
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iocell.suggestName(n)
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})
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iocell.io.o := castToBool(coreSignal)
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iocell.io.o := castToBool(coreSignal)
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iocell.io.oe := true.B
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iocell.io.oe := true.B
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padSignal := castFromBool(iocell.io.pad)
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padSignal := castFromBool(iocell.io.pad)
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@@ -215,7 +231,9 @@ object IOCell {
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// Note that we are relying on chisel deterministically naming this in the index order (which it does)
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// Note that we are relying on chisel deterministically naming this in the index order (which it does)
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// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
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// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
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// An alternative solution would be to suggestName(n + "_" + i)
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// An alternative solution would be to suggestName(n + "_" + i)
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name.foreach(n => iocell.suggestName(n))
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name.foreach(n => {
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iocell.suggestName(n)
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})
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iocell.io.pad := sig
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iocell.io.pad := sig
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iocell.io.ie := true.B
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iocell.io.ie := true.B
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iocell
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iocell
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@@ -230,7 +248,9 @@ object IOCell {
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// Note that we are relying on chisel deterministically naming this in the index order (which it does)
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// Note that we are relying on chisel deterministically naming this in the index order (which it does)
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// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
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// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
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// An alternative solution would be to suggestName(n + "_" + i)
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// An alternative solution would be to suggestName(n + "_" + i)
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name.foreach(n => iocell.suggestName(n))
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name.foreach(n => {
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iocell.suggestName(n)
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})
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iocell.io.o := sig
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iocell.io.o := sig
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iocell.io.oe := true.B
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iocell.io.oe := true.B
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iocell
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iocell
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@@ -33,7 +33,7 @@ trait TapeoutCli {
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parser.note("Tapeout specific options")
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parser.note("Tapeout specific options")
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Seq(
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Seq(
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OutAnnoAnnotation,
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OutAnnoAnnotation
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).foreach(_.addOptions(parser))
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).foreach(_.addOptions(parser))
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}
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}
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