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Fix UARTAdapter div bits

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This commit is contained in:
Jerry Zhao
2023-10-12 15:37:03 -07:00
parent 3cbcf6b6e8
commit deab3b11b6
1 changed files with 1 additions and 1 deletions
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2
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -42,7 +42,7 @@ class WithGPIOTiedOff extends HarnessBinder({
// DOC include start: WithUARTAdapter // DOC include start: WithUARTAdapter
class WithUARTAdapter extends HarnessBinder({ class WithUARTAdapter extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTPort) => { case (th: HasHarnessInstantiators, port: UARTPort) => {
val div = (th.getHarnessBinderClockFreqMHz * 1000000 / port.io.c.initBaudRate.toDouble).toInt val div = (th.getHarnessBinderClockFreqMHz.toDouble * 1000000 / port.io.c.initBaudRate.toDouble).toInt
val uart_sim = Module(new UARTAdapter(port.uartNo, div, false)).suggestName(s"uart_sim_uartno${port.uartNo}") val uart_sim = Module(new UARTAdapter(port.uartNo, div, false)).suggestName(s"uart_sim_uartno${port.uartNo}")
uart_sim.io.uart.txd := port.io.txd uart_sim.io.uart.txd := port.io.txd
port.io.rxd := uart_sim.io.uart.rxd port.io.rxd := uart_sim.io.uart.rxd