Merge pull request #1854 from ucb-bar/chisel6-attempt2

Support Chisel6 for RTL-sim/VLSI/FPGA flows

.github/scripts/check-commit.sh

@@ -45,21 +45,11 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
 dir="generators"
 branches=("master" "main" "dev")
 search
 
-submodules=("esp-tools-feedstock")
-dir="toolchains/esp-tools"
-branches=("main")
-search
-
-submodules=("riscv-isa-sim" "riscv-pk" "riscv-tests")
-dir="toolchains/esp-tools"
-branches=("master")
-search
-
 submodules=("riscv-tools-feedstock")
 dir="toolchains/riscv-tools"
 branches=("main")
@@ -92,7 +82,7 @@ dir="software"
 branches=("master" "dev")
 search
 
-submodules=("DRAMSim2" "axe" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
+submodules=("DRAMSim2" "axe" "dsptools" "dsptools-chisel3" "rocket-dsp-utils" "torture" "fixedpoint" "fixedpoint-chisel3" "cde" "midas-targetutils")
 dir="tools"
 branches=("master" "dev" "main")
 search

.github/scripts/defaults.sh

@@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
-grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
+grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
@@ -40,7 +40,6 @@ grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
 declare -A mapping
 mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig"
 mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
-mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
 mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
 mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig"
 mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
@@ -52,7 +51,6 @@ mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
 mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
 mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
 mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
-mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
 mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"

.github/scripts/run-tests.sh

@@ -77,9 +77,6 @@ case $1 in
     rocketchip)
         run_bmark
         ;;
-    chipyard-hwacha)
-        make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS
-        ;;
     chipyard-gemmini)
         GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
         rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
@@ -88,10 +85,6 @@ case $1 in
         run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal
         run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
         ;;
-    chipyard-sha3)
-        (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv
-        ;;
     chipyard-mempress)
         (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv

.github/workflows/chipyard-full-flow.yml

@@ -61,8 +61,8 @@ jobs:
               - '**/.gitignore'
               - '.github/ISSUE_TEMPLATE/**'
 
-  setup-repo:
-    name: setup-repo
+  full-flow:
+    name: full-flow
     needs: [change-filters, cancel-prior-workflows]
     if: needs.change-filters.outputs.needs-rtl == 'true'
     runs-on: as4
@@ -84,12 +84,6 @@ jobs:
           mkdir ${{ env.JAVA_TMP_DIR }}
           export MAKEFLAGS="-j32"
           ./build-setup.sh -v
-
-  run-cfg-finder:
-    name: run-cfg-finder
-    needs: [setup-repo]
-    runs-on: as4
-    steps:
       - name: Run config finder
         run: |
           cd ${{ env.REMOTE_WORK_DIR }}
@@ -97,12 +91,6 @@ jobs:
           source env.sh
           cd sims/verilator
           make find-config-fragments
-
-  run-tutorial:
-    name: run-tutorial
-    needs: [setup-repo]
-    runs-on: as4
-    steps:
       - name: Run smoke test
         run: |
           cd ${{ env.REMOTE_WORK_DIR }}
@@ -169,7 +157,7 @@ jobs:
 
   cleanup:
     name: cleanup
-    needs: [run-tutorial]
+    needs: [full-flow]
     runs-on: as4
     if: ${{ always() }}
     steps:

.github/workflows/chipyard-run-tests.yml

@@ -119,29 +119,6 @@ jobs:
             conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
             .github/scripts/check-commit.sh
 
-  tutorial-setup-check:
-    name: tutorial-setup-check
-    needs: [setup-complete]
-    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: as4
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Check that the tutorial-setup patches apply
-        run: |
-            conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
-            scripts/tutorial-setup.sh
-
   documentation-check:
     name: documentation-check
     needs: [setup-complete]
@@ -800,29 +777,6 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-llcchiplet"
 
-  chipyard-sha3-run-tests:
-    name: chipyard-sha3-run-tests
-    needs: prepare-chipyard-accels
-    runs-on: as4
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-accels"
-          project-key: "chipyard-sha3"
-
   chipyard-gemmini-run-tests:
     name: chipyard-gemmini-run-tests
     needs: prepare-chipyard-accels
@@ -1172,7 +1126,6 @@ jobs:
   all_tests_passed:
     name: "all tests passed"
     needs: [commit-on-master-check,
-            tutorial-setup-check,
             documentation-check,
             chipyard-rocket-run-tests,
             chipyard-hetero-run-tests,
@@ -1190,7 +1143,6 @@ jobs:
             chipyard-tethered-run-tests,
             chipyard-symmetric-run-tests,
             chipyard-llcchiplet-run-tests,
-            chipyard-sha3-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
             chipyard-prefetchers-run-tests,

.gitmodules

@@ -28,9 +28,6 @@
 [submodule "generators/hardfloat"]
 	path = generators/hardfloat
 	url = https://github.com/ucb-bar/berkeley-hardfloat.git
-[submodule "generators/hwacha"]
-	path = generators/hwacha
-	url = https://github.com/ucb-bar/hwacha.git
 [submodule "generators/ibex"]
 	path = generators/ibex
 	url = https://github.com/ucb-bar/ibex-wrapper.git
@@ -58,9 +55,6 @@
 [submodule "generators/rocket-chip-inclusive-cache"]
 	path = generators/rocket-chip-inclusive-cache
 	url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
-[submodule "generators/sha3"]
-	path = generators/sha3
-	url = https://github.com/ucb-bar/sha3.git
 [submodule "generators/shuttle"]
 	path = generators/shuttle
 	url = https://github.com/ucb-bar/shuttle.git
@@ -88,18 +82,6 @@
 [submodule "software/spec2017"]
 	path = software/spec2017
 	url = https://github.com/ucb-bar/spec2017-workload.git
-[submodule "toolchains/esp-tools/esp-tools-feedstock"]
-	path = toolchains/esp-tools/esp-tools-feedstock
-	url = https://github.com/ucb-bar/esp-tools-feedstock.git
-[submodule "toolchains/esp-tools/riscv-isa-sim"]
-	path = toolchains/esp-tools/riscv-isa-sim
-	url = https://github.com/ucb-bar/esp-isa-sim.git
-[submodule "toolchains/esp-tools/riscv-pk"]
-	path = toolchains/esp-tools/riscv-pk
-	url = https://github.com/riscv-software-src/riscv-pk.git
-[submodule "toolchains/esp-tools/riscv-tests"]
-	path = toolchains/esp-tools/riscv-tests
-	url = https://github.com/ucb-bar/esp-tests.git
 [submodule "toolchains/libgloss"]
 	path = toolchains/libgloss
 	url = https://github.com/ucb-bar/libgloss-htif.git
@@ -133,11 +115,11 @@
 [submodule "tools/circt"]
 	path = tools/circt
 	url = https://github.com/llvm/circt.git
-[submodule "tools/dsptools"]
-	path = tools/dsptools
+[submodule "tools/dsptools-fixedpoint"]
+	path = tools/dsptools-chisel3
 	url = https://github.com/ucb-bar/dsptools.git
-[submodule "tools/fixedpoint"]
-	path = tools/fixedpoint
+[submodule "tools/fixedpoint-chisel3"]
+	path = tools/fixedpoint-chisel3
 	url = https://github.com/ucb-bar/fixedpoint.git
 [submodule "tools/install-circt"]
 	path = tools/install-circt
@@ -151,3 +133,13 @@
 [submodule "vlsi/hammer-mentor-plugins"]
 	path = vlsi/hammer-mentor-plugins
 	url = https://github.com/ucb-bar/hammer-mentor-plugins.git
+[submodule "tools/dsptools"]
+	path = tools/dsptools
+	url = https://github.com/ucb-bar/dsptools.git
+[submodule "tools/fixedpoint"]
+	path = tools/fixedpoint
+	url = https://github.com/ucb-bar/fixedpoint.git
+[submodule "tools/midas-targetutils"]
+	path = tools/midas-targetutils
+	url = https://github.com/firesim/midas-targetutils.git
+

README.md

@@ -16,7 +16,7 @@ To get started using Chipyard, see the stable documentation on the Chipyard docu
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -65,7 +65,6 @@ These additional publications cover many of the internal components used in Chip
     * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://old.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
       * **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
       * **COBRA (BOOM Branch Prediction)**: J. Zhao, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408173).
-    * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
     * **Gemmini**: H. Genc, et al., *DAC'21*. [PDF](https://arxiv.org/pdf/1911.09925).
 * **Sims**
     * **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf).
@@ -87,7 +86,6 @@ These additional publications cover many of the internal components used in Chip
 
 This work is supported by the NSF CCRI ENS Chipyard Award #2016662.
 
-[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
 [hammer]:https://github.com/ucb-bar/hammer
 [firesim]:https://fires.im
 [ucb-bar]: http://bar.eecs.berkeley.edu

build.sbt

@@ -1,5 +1,9 @@
 import Tests._
 
+val chisel6 = sys.env.get("USE_CHISEL6").isDefined
+val chiselTestVersion = if (chisel6) "6.0.0" else "0.6.0"
+val scalaVersionFromChisel = if (chisel6) "2.13.12" else "2.13.10"
+
 // This gives us a nicer handle to the root project instead of using the
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))
@@ -11,7 +15,7 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
     case p: Project => p.name
     case l: Library => l.moduleCoord.name
   }
-  if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
+  if (Seq("firrtl", "chisel3", "chisel").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
     dep.target
   } else {
     "renamed/" + dep.target
@@ -21,11 +25,13 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.6",
-  scalaVersion := "2.13.10",
+  scalaVersion := scalaVersionFromChisel,
   assembly / test := {},
   assembly / assemblyMergeStrategy := {
     case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("chisel", "stage", xs @ _*) => chiselFirrtlMergeStrategy
     case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("META-INF", _*) => MergeStrategy.discard
     // should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
     case x if x.endsWith("module-info.class") => MergeStrategy.discard
     case x =>
@@ -35,6 +41,7 @@ lazy val commonSettings = Seq(
   scalacOptions ++= Seq(
     "-deprecation",
     "-unchecked",
+    "-Ytasty-reader",
     "-Ymacro-annotations"), // fix hierarchy API
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
   allDependencies := {
@@ -85,13 +92,22 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.6.0"
 
-lazy val chiselSettings = Seq(
-  libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
-  "org.apache.commons" % "commons-lang3" % "3.12.0",
-  "org.apache.commons" % "commons-text" % "1.9"),
-  addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
+lazy val chisel6Settings = Seq(
+  libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % "6.0.0"),
+  addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)
+)
+lazy val chisel3Settings = Seq(
+  libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"),
+  addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
+)
+
+lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq(
+  libraryDependencies ++= Seq(
+    "org.apache.commons" % "commons-lang3" % "3.12.0",
+    "org.apache.commons" % "commons-text" % "1.9"
+  )
+)
 
 
 // Subproject definitions begin
@@ -100,8 +116,8 @@ lazy val chiselSettings = Seq(
 
 lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
   .settings(chiselSettings)
-  .dependsOn(midasTargetUtils)
   .settings(commonSettings)
+  .dependsOn(if (chisel6) midasStandaloneTargetUtils else midasTargetUtils)
   .settings(
     libraryDependencies ++= Seq(
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
@@ -133,11 +149,6 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
       "org.scala-graph" %% "graph-core" % "1.13.5"
     )
   )
-  .settings( // Settings for scalafix
-    semanticdbEnabled := true,
-    semanticdbVersion := scalafixSemanticdb.revision,
-    scalacOptions += "-Ywarn-unused"
-  )
 lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 
 
@@ -145,19 +156,21 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 
 // Contains annotations & firrtl passes you may wish to use in rocket-chip without
 // introducing a circular dependency between RC and MIDAS
-
 lazy val midasTargetUtils = (project in file ("sims/firesim/sim/midas/targetutils"))
   .settings(commonSettings)
   .settings(chiselSettings)
+lazy val midasStandaloneTargetUtils = (project in file("tools/midas-targetutils"))
+  .settings(commonSettings)
+  .settings(chiselSettings)
 
 lazy val testchipip = (project in file("generators/testchipip"))
   .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+val stageDir = if (chisel6) "tools/stage/src/main/scala" else "tools/stage-chisel3/src/main/scala"
 lazy val chipyard = (project in file("generators/chipyard"))
-  .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
-    sha3, // On separate line to allow for cleaner tutorial-setup patches
+  .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes)
@@ -167,10 +180,11 @@ lazy val chipyard = (project in file("generators/chipyard"))
       "org.reflections" % "reflections" % "0.10.2"
     )
   )
- .settings(commonSettings)
+  .settings(commonSettings)
+  .settings(Compile / unmanagedSourceDirectories += file(stageDir))
 
 lazy val mempress = (project in file("generators/mempress"))
-  .dependsOn(rocketchip, midasTargetUtils)
+  .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -199,11 +213,6 @@ lazy val icenet = (project in file("generators/icenet"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val hwacha = (project in file("generators/hwacha"))
-  .dependsOn(rocketchip)
-  .settings(libraryDependencies ++= rocketLibDeps.value)
-  .settings(commonSettings)
-
 lazy val boom = freshProject("boom", file("generators/boom"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -229,12 +238,7 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sha3 = (project in file("generators/sha3"))
-  .dependsOn(rocketchip, midasTargetUtils)
-  .settings(libraryDependencies ++= rocketLibDeps.value)
-  .settings(commonSettings)
-
-lazy val gemmini = (project in file("generators/gemmini"))
+lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -245,7 +249,7 @@ lazy val nvdla = (project in file("generators/nvdla"))
   .settings(commonSettings)
 
 lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
-  .dependsOn(rocketchip, rocc_acc_utils, testchipip, midasTargetUtils)
+  .dependsOn(rocketchip, rocc_acc_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -255,21 +259,24 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
   .settings(commonSettings)
 
 lazy val tapeout = (project in file("./tools/tapeout/"))
-  .settings(chiselSettings)
+  .settings(chisel3Settings) // stuck on chisel3 and SFC
   .settings(commonSettings)
+  .settings(scalaVersion := "2.13.10") // stuck on chisel3 2.13.10
   .settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2"))
 
-lazy val fixedpoint = (project in file("./tools/fixedpoint/"))
+val fixedpointDir = if (chisel6) "./tools/fixedpoint" else "./tools/fixedpoint-chisel3"
+lazy val fixedpoint = freshProject("fixedpoint", file(fixedpointDir))
   .settings(chiselSettings)
   .settings(commonSettings)
 
-lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
+val dsptoolsDir = if (chisel6) "./tools/dsptools" else "./tools/dsptools-chisel3"
+lazy val dsptools = freshProject("dsptools", file(dsptoolsDir))
   .dependsOn(fixedpoint)
   .settings(
     chiselSettings,
     commonSettings,
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chiseltest" % "0.6.0",
+      "edu.berkeley.cs" %% "chiseltest" % chiselTestVersion,
       "org.scalatest" %% "scalatest" % "3.2.+" % "test",
       "org.typelevel" %% "spire" % "0.18.0",
       "org.scalanlp" %% "breeze" % "2.1.0",

common.mk

@@ -86,7 +86,7 @@ CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are init
 
 SCALA_EXT = scala
 VLOG_EXT = sv v
-CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
+CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim/src sims/firesim/sim/firesim-lib sims/firesim/sim/midas fpga/fpga-shells fpga/src tools/stage tools/stage-chisel3)
 CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT))
 CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT))
 TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout)

conda-reqs/esp-tools.yaml

@@ -1,18 +0,0 @@
-channels:
-    - ucb-bar
-    - conda-forge
-    - litex-hub
-    - nodefaults
-
-platforms:
-    - linux-64
-
-dependencies:
-    # https://conda-forge.org/feedstock-outputs/
-    #   filterable list of all conda-forge packages
-    # https://conda-forge.org/#contribute
-    #   instructions on adding a recipe
-    # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
-    #   documentation on package_spec syntax for constraining versions
-
-    - esp-tools==1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/esp-tools-feedstock

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -31,19 +31,9 @@ Processor Cores
 Accelerators
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-**Hwacha**
-  A decoupled vector architecture co-processor.
-  Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model.
-  Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface.
-  See :ref:`Generators/Hwacha:Hwacha` for more information.
-
 **Gemmini**
   A matrix-multiply accelerator targeting neural-networks
 
-**SHA3**
-  A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the
-  Chipyard integration flows using the RoCC interface.
-
 System Components:
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -95,10 +85,6 @@ Toolchains
   The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.).
   Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework.
 
-**esp-tools**
-  A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension.
-  This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.)
-
 Software
 -------------------------------------------
 

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -63,11 +63,7 @@ Start by checking out the proper Chipyard version. Run:
     # note: this may not be the latest release if the documentation version != "stable"
     git checkout |version|
 
-Next run the following script to fully setup Chipyard with a specific toolchain.
-There are two toolchains, one for normal RISC-V programs called ``riscv-tools`` which is the one needed for most Chipyard use-cases, and another for Hwacha called ``esp-tools``.
-Run the following script based off which compiler you would like to use.
-
-.. Note:: Prior versions of Chipyard recommended ``esp-tools`` for Gemmini development. Gemmini should now be used with the standard ``riscv-tools``.
+Next run the following script to fully setup Chipyard with the ``riscv-tools`` toolchain.
 
 .. Warning:: The following script will complete a "full" installation of Chipyard which may take a long time depending on the system.
     Ensure that this script completes fully (no interruptions) before continuing on. User can use the ``--skip`` or ``-s`` flag to skip steps:
@@ -96,7 +92,7 @@ Run the following script based off which compiler you would like to use.
 
 .. code-block:: shell
 
-    ./build-setup.sh riscv-tools # or esp-tools
+    ./build-setup.sh riscv-tools
 
 This script wraps around the conda environment initialization process, initializes all submodules (with the ``init-submodules-no-riscv-tools.sh`` script), installs a toolchain, and runs other setups.
 See ``./build-setup.sh --help`` for more details on what this does and how to disable parts of the setup.
@@ -107,7 +103,7 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
 
 .. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
 
-.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock and https://github.com/ucb-bar/esp-tools-feedstock repositories (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
+.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
 
 By running the following command you should see a environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.
 

docs/Customization/Custom-Chisel.rst

@@ -59,8 +59,8 @@ should look something like this:
 .. code-block:: scala
 
     lazy val chipyard = (project in file("generators/chipyard"))
-        .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
-            sha3, dsptools, `rocket-dsp-utils`,
+        .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
+            dsptools, `rocket-dsp-utils`,
             gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
             yourproject, // <- added to the middle of the list for simplicity
             constellation, mempress)

docs/Customization/Heterogeneous-SoCs.rst

@@ -4,7 +4,7 @@ Heterogeneous SoCs
 ===============================
 
 The Chipyard framework involves multiple cores and accelerators that can be composed in arbitrary ways.
-This discussion will focus on how you combine Rocket, BOOM and Hwacha in particular ways to create a unique SoC.
+This discussion will focus on how you combine Rocket and BOOM in particular ways to create a unique SoC.
 
 Creating a Rocket and BOOM System
 -------------------------------------------
@@ -21,40 +21,6 @@ The following example shows a dual core BOOM with a single core Rocket.
     :end-before: DOC include end: DualBoomAndSingleRocket
 
 
-Adding Hwachas
--------------------------------------------
-
-Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter.
-An example of adding a Hwacha to all tiles in the system is below.
-
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala
-    :language: scala
-    :start-after: DOC include start: BoomAndRocketWithHwacha
-    :end-before: DOC include end: BoomAndRocketWithHwacha
-
-In this example, Hwachas are added to both BOOM tiles and to the Rocket tile.
-All with the same Hwacha parameters.
-
-Assigning Accelerators to Specific Tiles with MultiRoCC
--------------------------------------------------------
-
-Located in ``generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC.
-Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile.
-For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles.
-An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached.
-
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala
-    :language: scala
-    :start-after: DOC include start: DualBoomAndRocketOneHwacha
-    :end-before: DOC include end: DualBoomAndRocketOneHwacha
-
-The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``0`` corresponds to the Rocket core).
-Finally, the ``WithMultiRoCC`` config fragment is called.
-This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
-This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.
-If this is used earlier in the configuration sequence, then MultiRoCC does not work.
-
-This config fragment can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``).
 
 Since config fragments are applied from right-to-left (or bottom-to-top as they are formatted here), the right-most config fragment specifying a core (which is ``freechips.rocketchip.subsystem.WithNBigCores`` in the example above) gets the first hart ID.
 Consider this config:

docs/Generators/Hwacha.rst

@@ -1,15 +0,0 @@
-Hwacha
-====================================
-
-The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
-The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven
-The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
-
-For more information on the Hwacha project, please visit the `Hwacha website <https://bar.eecs.berkeley.edu/projects/hwacha.html>`__ or search for "Krste Asanovic Hwacha" on Google Scholar for publications.
-
-To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache).
-
-To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala <https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/configs.scala>`__ to see the possible configuration parameters.
-
-Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions.
-To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it.

docs/Generators/SHA3.rst

@@ -1,81 +0,0 @@
-SHA3 RoCC Accelerator
-===================================
-The SHA3 accelerator is a basic RoCC accelerator for the SHA3 hashing algorithm.
-We like using SHA3 in Chipyard tutorial content because it is a self-contained, simple
-example of integrating a custom accelerator into Chipyard.
-
-
-Introduction
------------------------------------
-Secure hashing algorithms represent a class of hashing functions that provide four attributes: ease
-of hash computation, inability to generate the message from the hash (one-way property), inability
-to change the message and not the hash (weakly collision free property), and inability to find
-two messages with the same hash (strongly collision free property). The National Institute of
-Standards and Technology (NIST) recently held a competition for a new algorithm to be added to
-its set of Secure Hashing Algorithms (SHA). In 2012 the winner was determined to be the Keccak
-hashing function and a rough specification for SHA3 was established. The algorithm operates on
-variable length messages with a sponge function, and thus alternates between absorbing chunks of
-the message into a set of state bits and permuting the state. The absorbing is a simple bitwise
-XOR while the permutation is a more complex function composed of several operations, χ, θ, ρ,
-π, ι, that all perform various bitwise operations, including rotations, parity calculations, XORs,
-etc. The Keccak hashing function is parameterized for different sizes of state and message chunks
-but for this accelerator we will only support the Keccak-256 variant with 1600 bits of state and
-1088 bit message chunks. A diagram of the SHA3 accelerator is shown below.
-
-.. image:: ../_static/images/sha3.png
-
-Technical Details
-------------------------------------
-The accelerator is designed around three sub-systems, an
-interface with the processor, an interface with memory, and
-the actual hashing computation system. The interface
-with the processor is designed using the ROCC interface for
-coprocessors integrating with the RISC-V Rocket/BOOM
-processor. It includes the ability to transfer two 64 bit
-words to the co-processor, the request for a return value,
-and a small field for the function requested. The accelerator
-receives these requests using a ready/valid interface. The
-ROCC instruction is parsed and the needed information is
-stored into a execution context. The execution context contains
-the memory address of the message being hashed, the memory address
-to store the resulting hash in, the length of the message, and
-several other control fields.
-
-Once the execution context is valid the memory subsystem
-then begins to fetch chunks of the message. The memory
-subsystem is fully decoupled from the other subsystems
-and maintains a single full round memory buffers.
-The accelerators memory interface can provide a
-maximum of one 64 bit word per cycle which corresponds
-to 17 requests needed to fill a buffer (the size is dictated by
-the SHA3 algorithm). Memory requests to fill these buffers
-are sent out as rapidly as the memory interface can handle,
-with a tag field set to allow the different memory buffers
-requests to be distinguished, as they may be returned out of
-order. Once the memory subsystem has filled a buffer the
-control unit absorbs the buffer into the execution
-context, at which point the execution context is free to
-begin permutation, and the memory buffer is free to send
-more memory requests.
-
-After the buffer is absorbed, the hashing computation
-subsystem begins the permutation operations. Once
-the message is fully hashed, the hash is written to memory
-with a simple state machine.
-
-
-Using a SHA3 Accelerator
-------------------------
-Since the SHA3 accelerator is designed as a RoCC accelerator,
-it can be mixed into a Rocket or BOOM core by overriding the
-``BuildRoCC`` key. The config fragment is defined in the SHA3
-generator. An example configuration highlighting the use of
-this config fragment is shown here:
-
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
-   :language: scala
-   :start-after: DOC include start: Sha3Rocket
-   :end-before: DOC include end: Sha3Rocket
-
-The SHA3 example baremetal and Linux tests are located in the SHA3 repository.
-Please refer to its `README.md <https://github.com/ucb-bar/sha3/blob/master/README.md>`_ for more information on how to run/build the tests.

docs/Generators/index.rst

@@ -22,12 +22,10 @@ so changes to the generators themselves will automatically be used when building
    Rocket
    BOOM
    Constellation
-   Hwacha
    Gemmini
    IceNet
    TestChipIP
    Rocket-Chip-Generators
-   SHA3
    CVA6
    Ibex
    fft

docs/Simulation/Software-RTL-Simulation.rst

@@ -155,13 +155,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use:
     ./simulator-<yourproject>-<yourconfig> ...
 
 
-All ``make`` targets that can be applied to the default example, can also be applied to custom project using the custom environment variables. For example, the following code example will run the RISC-V assembly benchmark suite on the Hwacha subproject:
-
-.. code-block:: shell
-
-    make SUB_PROJECT=hwacha run-asm-tests
-
-
 Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral while the generated Verilog source files resides in ``generated-src/<...>-<package>-<config>/gen-collateral`` for the build/simulation.
 Specifically, for ``CONFIG=RocketConfig`` the SoC top-level (``TOP``) Verilog file is ``ChipTop.sv`` while the (``Model``) file is ``TestHarness.sv``.
 

fpga/Makefile

@@ -87,6 +87,8 @@ ifeq ($(SUB_PROJECT),arty100t)
 	FPGA_BRAND        ?= xilinx
 endif
 
+export USE_CHISEL6=1
+
 include $(base_dir)/variables.mk
 
 # default variables to build the arty example

fpga/src/main/scala/arty/IOBinders.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.arty
 
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 

fpga/src/main/scala/vc707/TestHarness.scala

@@ -1,6 +1,5 @@
 package chipyard.fpga.vc707
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.vcu118
 
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -12,36 +12,6 @@ class LargeBoomAndRocketConfig extends Config(
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-// DOC include start: BoomAndRocketWithHwacha
-class HwachaLargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
-  new boom.v3.common.WithNLargeBooms(1) ++                      // add 1 boom core
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: BoomAndRocketWithHwacha
-
-class LargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
-  new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
-  new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.v3.common.WithNLargeBooms(1) ++                                 // add 1 boom core
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
-// DOC include start: DualBoomAndRocketOneHwacha
-class DualLargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
-  new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
-  new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.v3.common.WithNLargeBooms(2) ++                                 // add 2 boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: DualBoomAndRocketOneHwacha
-
 class DualLargeBoomAndDualRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores

generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala

@@ -33,13 +33,6 @@ class LeanGemminiPrintfRocketConfig extends Config(
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class HwachaRocketConfig extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
 class MempressRocketConfig extends Config(
   new mempress.WithMemPress ++                                    // use Mempress (memory traffic generation) accelerator
   new chipyard.config.WithExtMemIdBits(7) ++                      // use 7 bits for tl like request id
@@ -50,13 +43,6 @@ class MempressRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class HwachaLargeBoomV3Config extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new boom.v3.common.WithNLargeBooms(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
 class AES256ECBRocketConfig extends Config(
   new aes.WithAES256ECBAccel ++                                   // use Caliptra AES 256 ECB accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++

generators/chipyard/src/main/scala/config/RocketSha3Configs.scala

@@ -1,22 +0,0 @@
-package chipyard
-
-import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
-
-// --------------
-// Rocket+SHA3 Configs
-// These live in a separate file to simplify patching out for the tutorials.
-// --------------
-
-// DOC include start: Sha3Rocket
-class Sha3RocketConfig extends Config(
-  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: Sha3Rocket
-
-class Sha3RocketPrintfConfig extends Config(
-  new sha3.WithSha3Printf ++
-  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/TutorialConfigs.scala

@@ -12,10 +12,6 @@ import scala.collection.immutable.ListMap
 // For each of 4 phases, participants will customize and build a
 // small demonstration config.
 
-// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh,
-// which removes the SHA3 accelerator RTL, and provides participants
-// the experience of integrating external RTL.
-
 // This file was originally developed for the cancelled ASPLOS-2020
 // Chipyard tutorial. While the configs here work, the corresponding
 // slideware has not yet been created.
@@ -54,26 +50,6 @@ class TutorialMMIOConfig extends Config(
   new chipyard.config.AbstractConfig
 )
 
-// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator
-class TutorialSha3Config extends Config(
-  // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo
-  // new sha3.WithSha3Accel ++
-
-  // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig
-)
-
-// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator
-class TutorialSha3BlackBoxConfig extends Config(
-  // Uncomment these lines once SHA3 is integrated
-  // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl
-  // new sha3.WithSha3Accel ++
-
-  // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig
-)
 
 // Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
 class TutorialNoCConfig extends Config(

generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala

@@ -6,7 +6,6 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.diplomacy._
 
-import hwacha.{Hwacha}
 import gemmini._
 
 import chipyard.{TestSuitesKey, TestSuiteHelper}
@@ -34,47 +33,6 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
   }
 })
 
-/**
- * Config fragment to add Hwachas to cores based on hart
- *
- * For ex:
- *   Core 0, 1, 2, 3 have been defined earlier
- *     with tileIds of 0, 1, 2, 3 respectively
- *   And you call WithMultiRoCCHwacha(0,1)
- *   Then Core 0 and 1 will get a Hwacha
- *
- * @param harts harts to specify which will get a Hwacha
- */
-class WithMultiRoCCHwacha(harts: Int*) extends Config(
-  new chipyard.config.WithHwachaTest ++
-  new Config((site, here, up) => {
-    case MultiRoCCKey => {
-      up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-        (i -> Seq((p: Parameters) => {
-          val hwacha = LazyModule(new Hwacha()(p))
-          hwacha
-        }))
-      }
-    }
-  })
-)
-
-class WithHwachaTest extends Config((site, here, up) => {
-  case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
-    up(TestSuitesKey).apply(tileParams, suiteHelper, p)
-    import hwacha.HwachaTestSuites._
-    suiteHelper.addSuites(rv64uv.map(_("p")))
-    suiteHelper.addSuites(rv64uv.map(_("vp")))
-    suiteHelper.addSuite(rv64sv("p"))
-    suiteHelper.addSuite(hwachaBmarks)
-    "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
-  }
-})
-
-/**
-  * The MultiRoCCGemmini fragment functions similarly to the
-  * WithMultiRoCCHwacha fragment defined above
-  */
 class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data](
   harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => {
   case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i =>

scripts/build-setup.sh

@@ -12,11 +12,10 @@ source $CYDIR/scripts/utils.sh
 common_setup
 
 usage() {
-    echo "Usage: ${0} [OPTIONS] [riscv-tools | esp-tools]"
+    echo "Usage: ${0} [OPTIONS] [riscv-tools]"
     echo ""
     echo "Installation Types"
     echo "  riscv-tools: if set, builds the riscv toolchain (this is also the default)"
-    echo "  esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator"
     echo ""
     echo "Helper script to fully initialize repository that wraps other scripts."
     echo "By default it initializes/installs things in the following order:"
@@ -69,7 +68,7 @@ do
     case $1 in
         -h | --help )
             usage 3 ;;
-        riscv-tools | esp-tools)
+        riscv-tools )
             TOOLCHAIN_TYPE=$1 ;;
         --verbose | -v)
             VERBOSE_FLAG=$1
@@ -119,29 +118,6 @@ run_step() {
 
 {
 
-# esp-tools should ONLY be used for hwacha.
-# Check for this, since many users will be attempting to use this with gemmini
-if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
-    while true; do
-        printf '\033[2J'
-        read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
-        case "$validate" in
-            y | Y)
-                echo "Installing esp-tools."
-                break
-                ;;
-            n | N)
-                error "Rerun with riscv-tools"
-                exit 3
-                ;;
-            *)
-                error "Invalid response. Please type \"y\" or \"n\""
-                ;;
-        esac
-    done
-fi
-
-
 #######################################
 ###### BEGIN STEP-BY-STEP SETUP #######
 #######################################

scripts/build-toolchain-extra.sh

@@ -16,11 +16,10 @@ common_setup
 readonly MAKE
 
 usage() {
-    echo "usage: ${0} [OPTIONS] [riscv-tools | esp-tools]"
+    echo "usage: ${0} [OPTIONS] [riscv-tools]"
     echo ""
     echo "Installation Types"
     echo "   riscv-tools: if set, builds the riscv toolchain (this is also the default)"
-    echo "   esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator"
     echo ""
     echo "Options"
     echo "   --prefix -p PREFIX    : Install destination."
@@ -45,7 +44,7 @@ do
             RISCV=$(realpath $1) ;;
         --clean-after-install )
             CLEANAFTERINSTALL="true" ;;
-        riscv-tools | esp-tools)
+        riscv-tools )
             TOOLCHAIN=$1 ;;
         * )
             error "invalid option $1"

scripts/generate-conda-lockfiles.sh

@@ -10,7 +10,7 @@ if [ ! -d "$REQS_DIR" ]; then
   exit 1
 fi
 
-for TOOLCHAIN_TYPE in riscv-tools esp-tools; do
+for TOOLCHAIN_TYPE in riscv-tools; do
     # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
     LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
     rm -rf $LOCKFILE

scripts/init-submodules-no-riscv-tools-nolog.sh

@@ -72,7 +72,6 @@ cd "$RDIR"
             generators/cva6 \
             generators/nvdla \
             toolchains/libgloss \
-            generators/sha3 \
             generators/gemmini \
             generators/rocket-chip \
             sims/firesim \
@@ -101,9 +100,6 @@ cd "$RDIR"
 )
 
 (
-    # Non-recursive clone to exclude riscv-linux
-    git submodule update --init generators/sha3
-
     # Non-recursive clone to exclude cva6 submods
     git submodule update --init generators/cva6
     git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6

scripts/repo-clean.sh

@@ -9,9 +9,6 @@ rm -rf $RDIR/toolchains/libgloss/build.log
 rm -rf $RDIR/toolchains/riscv-tools/riscv-isa-sim/build.log
 rm -rf $RDIR/toolchains/riscv-tools/riscv-pk/build.log
 rm -rf $RDIR/toolchains/riscv-tools/riscv-tests/build.log
-rm -rf $RDIR/toolchains/esp-tools/riscv-isa-sim/build.log
-rm -rf $RDIR/toolchains/esp-tools/riscv-pk/build.log
-rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
 (
     pushd $RDIR/generators/constellation
     if [ -d espresso ]

scripts/tutorial-patches/build.sbt.patch

@@ -1,28 +0,0 @@
-diff --git a/build.sbt b/build.sbt
-index c3be6161..2a6d7160 100644
---- a/build.sbt
-+++ b/build.sbt
-@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
- 
- lazy val chipyard = (project in file("generators/chipyard"))
-   .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache,
--    sha3, // On separate line to allow for cleaner tutorial-setup patches
-+    //sha3, // On separate line to allow for cleaner tutorial-setup patches
-     dsptools, rocket_dsp_utils,
-     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-     constellation, mempress, barf, shuttle, caliptra_aes)
-@@ -219,10 +219,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
-   .settings(libraryDependencies ++= rocketLibDeps.value)
-   .settings(commonSettings)
- 
--lazy val sha3 = (project in file("generators/sha3"))
--  .dependsOn(rocketchip, midasTargetUtils)
--  .settings(libraryDependencies ++= rocketLibDeps.value)
--  .settings(commonSettings)
-+// lazy val sha3 = (project in file("generators/sha3"))
-+//   .dependsOn(rocketchip, midasTargetUtils)
-+//   .settings(libraryDependencies ++= rocketLibDeps.value)
-+//   .settings(commonSettings)
- 
- lazy val gemmini = (project in file("generators/gemmini"))
-   .dependsOn(rocketchip)

scripts/tutorial-setup.sh

@@ -1,16 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-RDIR=$(git rev-parse --show-toplevel)
-
-cd $RDIR
-
-git rm generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
-git rm -rf generators/sha3
-
-for p in scripts/tutorial-patches/*.patch
-do
-    echo "Applying tutorial patch $p"
-    git apply $p
-done

sims/common-sim-flags.mk

@@ -2,17 +2,9 @@
 # common gcc configuration/optimization
 #----------------------------------------------------------------------------------------
 SIM_OPT_CXXFLAGS := -O3
-
-# Workaround: esp-isa-sim doesn't install libriscv,
-# so don't link with libriscv if it doesn't exist
-# potentially breaks some configs
-
-ifeq (,$(wildcard $(RISCV)/lib/libriscv.so))
-$(warning libriscv not found)
-LRISCV=
-else
 LRISCV=-lriscv
-endif
+
+export USE_CHISEL6=1
 
 SIM_CXXFLAGS = \
 	$(CXXFLAGS) \

tools/stage/src/main/scala/ChipyardAnnotations.scala

@@ -0,0 +1,66 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import chisel3.experimental.BaseModule
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{HasShellOptions, ShellOption, Unserializable}
+
+trait ChipyardOption extends Unserializable { this: Annotation => }
+
+/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format  */
+private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "legacy-configs",
+      toAnnotationSeq = a => {
+        val split = a.split(':')
+        assert(split.length == 2, s"'${a}' split by ':' doesn't yield two things")
+        val packageName = split.head
+        val configs     = split.last.split("_")
+        Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } ))
+      },
+      helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).",
+      shortOption = Some("LC")
+    )
+  )
+}
+
+/** Paths to config classes */
+case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object ConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[Seq[String]](
+      longOption = "configs",
+      toAnnotationSeq = a => Seq(ConfigsAnnotation(a)),
+      helpText = "<comma-delimited configs>",
+      shortOption = Some("C")
+    )
+  )
+}
+
+case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object TopModuleAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "top-module",
+      toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])),
+      helpText = "<top module>",
+      shortOption = Some("T")
+    )
+  )
+}
+
+/** Optional base name for generated files' filenames */
+case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with ChipyardOption
+private[stage] object OutputBaseNameAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "name",
+      toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)),
+      helpText = "<base name of output files>",
+      shortOption = Some("n")
+    )
+  )
+}

tools/stage/src/main/scala/ChipyardCli.scala

@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import firrtl.options.Shell
+
+trait ChipyardCli { this: Shell =>
+
+  parser.note("Chipyard Generator Options")
+  Seq(
+    TopModuleAnnotation,
+    ConfigsAnnotation,
+    OutputBaseNameAnnotation,
+    UnderscoreDelimitedConfigsAnnotation
+  ).foreach(_.addOptions(parser))
+}

tools/stage/src/main/scala/ChipyardOptions.scala

@@ -0,0 +1,40 @@
+// See LICENSE
+
+package chipyard.stage
+
+class ChipyardOptions private[stage] (
+                                         val topModule:         Option[Class[_ <: Any]] = None,
+                                         val configNames:       Option[Seq[String]] = None,
+                                         val outputBaseName:    Option[String] = None) {
+
+  private[stage] def copy(
+                           topModule:         Option[Class[_ <: Any]] = topModule,
+                           configNames:       Option[Seq[String]] = configNames,
+                           outputBaseName:    Option[String] = outputBaseName,
+                         ): ChipyardOptions = {
+
+    new ChipyardOptions(
+      topModule=topModule,
+      configNames=configNames,
+      outputBaseName=outputBaseName,
+    )
+  }
+
+  lazy val topPackage: Option[String] = topModule match {
+    case Some(a) => Some(a.getPackage.getName)
+    case _ => None
+  }
+
+  lazy val configClass: Option[String] = configNames match {
+    case Some(names) =>
+      val classNames = names.map{ n => n.split('.').last }
+      Some(classNames.mkString("_"))
+    case _ => None
+  }
+
+  lazy val longName: Option[String] = outputBaseName match {
+    case Some(name) => Some(name)
+    case _ =>
+      if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
+  }
+}

tools/stage/src/main/scala/ChipyardStage.scala

@@ -0,0 +1,71 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import circt.stage.{ChiselStage, CIRCTTargetAnnotation, CIRCTTarget}
+import firrtl.options.PhaseManager.PhaseDependency
+import firrtl.options.{Shell}
+import firrtl.{AnnotationSeq}
+import firrtl.options.{Phase, PhaseManager, Shell, Stage, StageError, StageMain, Dependency}
+
+final class ChipyardChiselStage extends ChiselStage {
+  override def run(annotations: AnnotationSeq): AnnotationSeq = {
+
+    val pm = new PhaseManager(
+      targets = Seq(
+        Dependency[chisel3.stage.phases.Checks],
+        Dependency[chisel3.stage.phases.AddImplicitOutputFile],
+        Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
+        Dependency[chisel3.stage.phases.MaybeAspectPhase],
+        Dependency[chisel3.stage.phases.AddSerializationAnnotations],
+        Dependency[chisel3.stage.phases.Convert],
+        Dependency[chisel3.stage.phases.AddDedupGroupAnnotations],
+        Dependency[chisel3.stage.phases.MaybeInjectingPhase],
+        Dependency[circt.stage.phases.AddImplicitOutputFile],
+        Dependency[circt.stage.phases.Checks],
+        Dependency[circt.stage.phases.CIRCT]
+      ),
+      currentState = Seq(
+        Dependency[firrtl.stage.phases.AddDefaults],
+        Dependency[firrtl.stage.phases.Checks]
+      )
+    )
+    pm.transform(annotations :+ CIRCTTargetAnnotation(CIRCTTarget.CHIRRTL))
+  }
+}
+
+class ChipyardStage extends ChiselStage {
+  override val shell = new Shell("chipyard") with ChipyardCli with circt.stage.CLI
+  override def run(annotations: AnnotationSeq): AnnotationSeq = {
+
+    val pm = new PhaseManager(
+      targets = Seq(
+        Dependency[chipyard.stage.phases.Checks],
+        Dependency[chipyard.stage.phases.TransformAnnotations],
+        Dependency[chipyard.stage.phases.PreElaboration],
+        Dependency[ChipyardChiselStage],
+        Dependency[chipyard.stage.phases.GenerateFirrtlAnnos],
+        Dependency[chipyard.stage.phases.AddDefaultTests],
+        Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
+        Dependency[chipyard.stage.phases.GenerateArtefacts],
+      ),
+      currentState = Seq(
+        Dependency[firrtl.stage.phases.AddDefaults],
+        Dependency[firrtl.stage.phases.Checks]
+      )
+    )
+    pm.transform(annotations)
+  }
+  // override val targets: Seq[PhaseDependency] = Seq(
+  //   Dependency[chipyard.stage.phases.Checks],
+  //   Dependency[chipyard.stage.phases.TransformAnnotations],
+  //   Dependency[chipyard.stage.phases.PreElaboration],
+  //   Dependency[ChipyardChiselStage],
+  //   Dependency[chipyard.stage.phases.GenerateFirrtlAnnos],
+  //   Dependency[chipyard.stage.phases.AddDefaultTests],
+  //   Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
+  //   Dependency[chipyard.stage.phases.GenerateArtefacts],
+  // )
+  override final def invalidates(a: Phase): Boolean = false
+}

tools/stage/src/main/scala/StageUtils.scala

@@ -0,0 +1,32 @@
+// See LICENSE
+
+package chipyard.stage
+
+import java.io.{File, FileWriter}
+
+import org.chipsalliance.cde.config.{Config, Parameters}
+import freechips.rocketchip.util.{BlackBoxedROM, ROMGenerator}
+
+trait HasChipyardStageUtils {
+
+  def getConfig(fullConfigClassNames: Seq[String]): Config = {
+    new Config(fullConfigClassNames.foldRight(Parameters.empty) { case (currentName, config) =>
+      val currentConfig = try {
+        Class.forName(currentName).newInstance.asInstanceOf[Config]
+      } catch {
+        case e: java.lang.ClassNotFoundException =>
+          throw new Exception(s"""Unable to find part "$currentName" from "$fullConfigClassNames", did you misspell it or specify the wrong package path?""", e)
+      }
+      currentConfig ++ config
+    })
+  }
+
+  def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
+    val f = new File(targetDir, fname)
+    val fw = new FileWriter(f)
+    fw.write(contents)
+    fw.close
+    f
+  }
+
+}

tools/stage/src/main/scala/package.scala

@@ -0,0 +1,24 @@
+// See LICENSE
+
+package chipyard
+
+import firrtl.AnnotationSeq
+import firrtl.options.OptionsView
+
+package object stage {
+
+  implicit object ChipyardOptionsView extends OptionsView[ChipyardOptions] {
+
+    def view(annotations: AnnotationSeq): ChipyardOptions = annotations
+      .collect { case a: ChipyardOption => a }
+      .foldLeft(new ChipyardOptions()){ (c, x) =>
+        x match {
+          case TopModuleAnnotation(a)         => c.copy(topModule = Some(a))
+          case ConfigsAnnotation(a)           => c.copy(configNames = Some(a))
+          case OutputBaseNameAnnotation(a)    => c.copy(outputBaseName = Some(a))
+        }
+      }
+
+  }
+
+}

tools/stage/src/main/scala/phases/AddDefaultTests.scala

@@ -0,0 +1,53 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage.phases
+
+import scala.util.Try
+import scala.collection.mutable
+
+import org.chipsalliance.cde.config.Parameters
+import chisel3.stage.phases.Elaborate
+import firrtl.AnnotationSeq
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options._
+import firrtl.options.Viewer._
+import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
+import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
+import freechips.rocketchip.tile.XLen
+
+import chipyard.TestSuiteHelper
+import chipyard.TestSuitesKey
+import chipyard.stage._
+
+/** Annotation that contains a list of [[RocketTestSuite]]s to run */
+case class ChipyardTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation with Unserializable
+
+
+class AddDefaultTests extends Phase with PreservesAll with HasChipyardStageUtils {
+  override val prerequisites = Seq(Dependency[ChipyardChiselStage])
+  override val optionalPrerequisiteOf = Seq(Dependency[GenerateTestSuiteMakefrags])
+
+  private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
+    val annotations = mutable.ArrayBuffer[Annotation]()
+    val suiteHelper = new TestSuiteHelper
+    // Use Xlen as a proxy for detecting if we are a processor-like target
+    // The underlying test suites expect this field to be defined
+    val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
+    if (p.lift(XLen).nonEmpty)
+      // If a custom test suite is set up, use the custom test suite
+      annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
+
+    ChipyardTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq
+  }
+
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val (testSuiteAnnos, oAnnos) = annotations.partition {
+      case ChipyardTestSuiteAnnotation(_)  => true
+      case o => false
+    }
+    implicit val p = getConfig(view[ChipyardOptions](annotations).configNames.get).toInstance
+    addTestSuiteAnnotations(p) ++ oAnnos
+  }
+}

tools/stage/src/main/scala/phases/Checks.scala

@@ -0,0 +1,47 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.annotations.Annotation
+import firrtl.options.{OptionsException, Phase, TargetDirAnnotation}
+import chipyard.stage._
+
+import scala.collection.mutable
+
+/** Checks for the correct type and number of command line arguments */
+class Checks extends Phase with PreservesAll {
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir, topModule, configNames, outputBaseName = mutable.ListBuffer[Annotation]()
+
+    annotations.foreach {
+      case a: TargetDirAnnotation      => a +=: targetDir
+      case a: TopModuleAnnotation      => a +=: topModule
+      case a: ConfigsAnnotation        => a +=: configNames
+      case a: OutputBaseNameAnnotation => a +=: outputBaseName
+      case _ =>
+    }
+
+    def required(annoList: mutable.ListBuffer[Annotation], option: String): Unit = {
+      if (annoList.size != 1) {
+        throw new OptionsException(s"Exactly one $option required")
+      }
+    }
+
+    def optional(annoList: mutable.ListBuffer[Annotation], option: String): Unit = {
+      if (annoList.size > 1) {
+        throw new OptionsException(s"Too many $option options have been specified")
+      }
+    }
+
+    required(targetDir, "target directory")
+    required(topModule, "top module")
+    required(configNames, "configs string (','-delimited)")
+
+    optional(outputBaseName, "output base name")
+
+    annotations
+  }
+
+}

tools/stage/src/main/scala/phases/GenerateArtefacts.scala

@@ -0,0 +1,26 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.options.{Dependency, Phase, StageOptions}
+import firrtl.options.Viewer.view
+import chipyard.stage._
+import freechips.rocketchip.util.{ElaborationArtefacts}
+
+/** Writes [[ElaborationArtefacts]] into files */
+class GenerateArtefacts extends Phase with PreservesAll with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir = view[StageOptions](annotations).targetDir
+
+    ElaborationArtefacts.files.foreach { case (extension, contents) =>
+      writeOutputFile(targetDir, s"${view[ChipyardOptions](annotations).longName.get}.${extension}", contents ())
+    }
+
+    annotations
+  }
+
+}

tools/stage/src/main/scala/phases/GenerateFirrtlAnnos.scala

@@ -0,0 +1,34 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.annotations.{JsonProtocol}
+import firrtl.options.Viewer.view
+import firrtl.options._
+import chipyard.stage._
+
+/** Writes FIRRTL annotations into a file */
+class GenerateFirrtlAnnos extends Phase with PreservesAll with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir = view[StageOptions](annotations).targetDir
+    val fileName = s"${view[ChipyardOptions](annotations).longName.get}.anno.json"
+
+    val annos = annotations.view.flatMap {
+      // Remove TargetDirAnnotation so that we can pass as argument to FIRRTL
+      // Remove CustomFileEmission, those are serialized automatically by Stages
+      case (_: Unserializable | _: TargetDirAnnotation | _: CustomFileEmission) =>
+        None
+      case a =>
+        Some(a)
+    }
+
+    writeOutputFile(targetDir, fileName, JsonProtocol.serialize(annos.toSeq))
+
+    annotations
+  }
+
+}

tools/stage/src/main/scala/phases/GenerateTestSuiteMakefrags.scala

@@ -0,0 +1,49 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage.phases
+
+import scala.collection.mutable
+
+import firrtl.AnnotationSeq
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{Phase, StageOptions, Unserializable, Dependency}
+import firrtl.options.Viewer.view
+import chipyard.stage._
+import freechips.rocketchip.system.TestGeneration
+
+trait MakefragSnippet { self: Annotation =>
+  def toMakefrag: String
+}
+
+case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
+
+/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
+class GenerateTestSuiteMakefrags extends Phase with HasChipyardStageUtils {
+
+  // Our annotations tend not to be serializable, but are not marked as such.
+  override val prerequisites = Seq(Dependency[chipyard.stage.phases.GenerateFirrtlAnnos],
+                                   Dependency[chipyard.stage.phases.AddDefaultTests])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir = view[StageOptions](annotations).targetDir
+    val fileName = s"${view[ChipyardOptions](annotations).longName.get}.d"
+
+    val makefragBuilder = new mutable.StringBuilder()
+    val outputAnnotations = annotations.flatMap {
+      case ChipyardTestSuiteAnnotation(tests) =>
+        // Unfortunately the gen method of TestGeneration is rocketchip package
+        // private, so we either have to copy code in or use the stateful form
+        TestGeneration.addSuites(tests)
+        None
+      case a: MakefragSnippet =>
+        makefragBuilder :+ ("\n" + a.toMakefrag)
+        None
+      case a => Some(a)
+    }
+    writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)
+    outputAnnotations
+  }
+
+  override final def invalidates(a: Phase): Boolean = false
+}

tools/stage/src/main/scala/phases/PreElaboration.scala

@@ -0,0 +1,43 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import chisel3.RawModule
+import chisel3.stage.ChiselGeneratorAnnotation
+import firrtl.AnnotationSeq
+import firrtl.options.Viewer.view
+import firrtl.options.{Dependency, Phase, StageOptions}
+import org.chipsalliance.cde.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import chipyard.stage._
+
+case object TargetDirKey extends Field[String](".")
+
+/** Constructs a generator function that returns a top module with given config parameters */
+class PreElaboration extends Phase with PreservesAll with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[Checks])
+  override val optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.phases.Elaborate])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+
+    val stageOpts = view[StageOptions](annotations)
+    val rOpts = view[ChipyardOptions](annotations)
+    val topMod = rOpts.topModule.get
+
+    val config = getConfig(rOpts.configNames.get).alterPartial {
+      case TargetDirKey => stageOpts.targetDir
+    }
+
+    val gen = () =>
+      topMod
+        .getConstructor(classOf[Parameters])
+        .newInstance(config) match {
+          case a: RawModule => a
+          case a: LazyModule => LazyModule(a).module
+        }
+
+    ChiselGeneratorAnnotation(gen) +: annotations
+  }
+
+}

tools/stage/src/main/scala/phases/PreservesAll.scala

@@ -0,0 +1,8 @@
+package chipyard.stage.phases
+
+import firrtl.AnnotationSeq
+import firrtl.options.{Dependency, DependencyManagerException, Phase, PhaseManager}
+
+trait PreservesAll { this: Phase =>
+  override def invalidates(phase: Phase) = false
+}

tools/stage/src/main/scala/phases/TransformAnnotations.scala

@@ -0,0 +1,21 @@
+// See LICENSE
+
+package chipyard.stage.phases
+
+import chisel3.stage.ChiselOutputFileAnnotation
+import firrtl.AnnotationSeq
+import firrtl.options.Viewer.view
+import firrtl.options.{Dependency, Phase}
+import chipyard.stage._
+
+/** Transforms RocketChipAnnotations into those used by other stages */
+class TransformAnnotations extends Phase with PreservesAll with HasChipyardStageUtils {
+
+  override val prerequisites = Seq(Dependency[Checks])
+  override val optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.phases.AddImplicitOutputFile])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    /** Construct output file annotation for emission */
+    new ChiselOutputFileAnnotation(view[ChipyardOptions](annotations).longName.get) +: annotations
+  }
+}

variables.mk

@@ -78,18 +78,6 @@ ifeq ($(SUB_PROJECT),chipyard)
 	TB                ?= TestDriver
 	TOP               ?= ChipTop
 endif
-# for Hwacha developers
-ifeq ($(SUB_PROJECT),hwacha)
-	SBT_PROJECT       ?= chipyard
-	MODEL             ?= TestHarness
-	VLOG_MODEL        ?= $(MODEL)
-	MODEL_PACKAGE     ?= freechips.rocketchip.system
-	CONFIG            ?= HwachaConfig
-	CONFIG_PACKAGE    ?= hwacha
-	GENERATOR_PACKAGE ?= chipyard
-	TB                ?= TestDriver
-	TOP               ?= ExampleRocketSystem
-endif
 # For TestChipIP developers running unit-tests
 ifeq ($(SUB_PROJECT),testchipip)
 	SBT_PROJECT       ?= chipyard
@@ -154,9 +142,6 @@ CHIPYARD_RSRCS_DIR   = $(base_dir)/generators/chipyard/src/main/resources
 # names of various files needed to compile and run things
 #########################################################################################
 long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
-ifeq ($(GENERATOR_PACKAGE),hwacha)
-	long_name=$(MODEL_PACKAGE).$(CONFIG)
-endif
 
 # classpaths
 CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache

vlsi/Makefile

@@ -45,6 +45,7 @@ VLSI_TOP           ?= $(TOP)
 VLSI_MODEL_DUT_NAME ?= chiptop0
 # If overriding, this should be relative to $(vlsi_dir)
 VLSI_OBJ_DIR       ?= build
+export USE_CHISEL6        = 1
 ifneq ($(CUSTOM_VLOG),)
 	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
 else