wu-arch/chipyard
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fix naming

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This commit is contained in:
Ella Schwarz
2024-01-01 13:16:53 -08:00
parent fcf9139009
commit e7ed33244a
3 changed files with 5 additions and 6 deletions
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5
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -23,7 +23,7 @@ class AbstractConfig extends Config(
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
new chipyard.harness.WithChipIdPinFromHarness ++ // drive chip id pin with a plusarg, if chip id pin is present
new chipyard.harness.WithDriveChipIdPin ++ // drive chip id pin from harness binder, if chip id pin is present
new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port
new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
@@ -37,7 +37,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithGPIOCells ++
new chipyard.iobinders.WithSPIFlashIOCells ++
new chipyard.iobinders.WithExtInterruptIOCells ++
new chipyard.iobinders.WithChipIdPin ++
new chipyard.iobinders.WithChipIdIOCells ++
new chipyard.iobinders.WithCustomBootPin ++
// The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO
// Instead, they directly pass through the DigitalTop ports to ports in the ChipTop
@@ -65,7 +65,6 @@ class AbstractConfig extends Config(
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
new testchipip.soc.WithChipIdPin ++ // add a chip id pin for setting chip id in multi-chip configs
new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface

4
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -252,8 +252,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
}
})
//TODO: Allow setting from harness with chipId argument, hardcoding is temporary hack
class WithChipIdPinFromHarness extends HarnessBinder({
//TODO: Set with chipId argument to harness binder, hardcoding is temporary hack
class WithDriveChipIdPin extends HarnessBinder({
case (th: HasHarnessInstantiators, port: ChipIdPort) => {
port.io := 0.U
}

2
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
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@@ -356,7 +356,7 @@ class WithSerialTLIOCells extends OverrideIOBinder({
}
})
class WithChipIdPin extends OverrideIOBinder({
class WithChipIdIOCells extends OverrideIOBinder({
(system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)