Fix HARNESS_* to MODEL_* for consistence
This commit is contained in:
joey0320
31
common.mk
31
common.mk
@@ -137,7 +137,7 @@ firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE)
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#########################################################################################
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# create verilog files rules and variables
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#########################################################################################
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FIRTOOL_TARGETS = \
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SFC_FIRTOOL_TARGETS = \
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$(FIRTOOL_SMEMS_CONF) \
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$(FIRTOOL_TOP_SMEMS_JSON) \
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$(FIRTOOL_TOP_HRCHY_JSON) \
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@@ -150,10 +150,17 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
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# DOC include start: FirrtlCompiler
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# This step can take either one of two paths. The first path is when SFC
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# compiles Chisel to CHIRRTL, and FIRTOOL compiles CHIRRTL to Verilog. Otherwise,
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# when custom FIRRTL transforms are included or if a Fixed type is used within
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# the dut, SFC compiles Chisel to LowFIRRTL and FIRTOOL compiles it to Verilog.
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# Users can indicate to the Makefile of custom FIRRTL transforms by setting the
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# "ENABLE_CUSTOM_FIRRTL_PASS" env variable.
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#
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# hack: lower to low firrtl if Fixed types are found
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# hack: when using dontTouch, io.cpu annotations are not removed by SFC,
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# hence we remove them manually by using jq before passing them to firtool
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$(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
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$(SFC_FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
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ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
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$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
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$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
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@@ -172,7 +179,7 @@ endif
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--allow-unrecognized-annotations \
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-X $(SFC_LEVEL) \
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$(EXTRA_FIRRTL_OPTIONS))
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-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE)
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-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
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@if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
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@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json; fi
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firtool \
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@@ -211,31 +218,31 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
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$(SED) -i 's/\.\///' $(BB_MODS_FILELIST)
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sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST)
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$(TOP_SMEMS_CONF) $(HARNESS_SMEMS_CONF) &: $(FIRTOOL_TOP_SMEMS_JSON) $(FIRTOOL_MODEL_SMEMS_JSON) $(FIRTOOL_SMEMS_CONF)
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$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(FIRTOOL_SMEMS_CONF) $(FIRTOOL_MODEL_HRCHY_JSON)
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$(base_dir)/scripts/split-mems-conf.py \
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--in-smems-conf $(FIRTOOL_SMEMS_CONF) \
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--in-model-hrchy-json $(FIRTOOL_MODEL_HRCHY_JSON) \
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--dut-module-name $(TOP) \
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--model-module-name $(MODEL) \
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--out-dut-smems-conf $(TOP_SMEMS_CONF) \
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--out-model-smems-conf $(HARNESS_SMEMS_CONF)
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--out-model-smems-conf $(MODEL_SMEMS_CONF)
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# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
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MACROCOMPILER_MODE ?= --mode synflops
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TOP_MACROCOMPILER_MODE ?= --mode synflops
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$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
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$(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE))
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$(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
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HARNESS_MACROCOMPILER_MODE = --mode synflops
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$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEMS_FILE)
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$(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE))
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MODEL_MACROCOMPILER_MODE = --mode synflops
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$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
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$(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
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########################################################################################
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# remove duplicate files and headers in list of simulation file inputs
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########################################################################################
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$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(HARNESS_SMEMS_FILE)
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$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE)
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sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
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echo "$(TOP_SMEMS_FILE)" >> $@
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echo "$(HARNESS_SMEMS_FILE)" >> $@
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echo "$(MODEL_SMEMS_FILE)" >> $@
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#########################################################################################
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# helper rule to just make verilog files
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@@ -64,7 +64,7 @@ As in the rest of the Chipyard flows, we specify our SoC configuration using the
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However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module.
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Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on.
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The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly.
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By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
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By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
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We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``.
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@@ -171,9 +171,9 @@ SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf
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TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
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TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v
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TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir
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HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
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HARNESS_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).harness.mems.v
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HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir
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MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf
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MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v
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MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir
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# top module files to include
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TOP_MODS_FILELIST ?= $(build_dir)/$(long_name).top.f
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@@ -28,9 +28,9 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
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SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
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ifdef USE_SRAM_COMPILER
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MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
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TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
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else
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MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
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TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
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endif
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ENV_YML ?= $(vlsi_dir)/env.yml
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@@ -121,12 +121,12 @@ SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
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SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
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include $(vlsi_dir)/sim.mk
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$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
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$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " top_module: $(VLSI_TOP)" >> $@
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echo " input_files:" >> $@
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for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
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for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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@@ -163,7 +163,7 @@ ifneq ($(BINARY), )
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endif
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echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
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$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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mkdir -p $(output_dir)
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echo "sim.inputs:" > $@
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@@ -186,7 +186,7 @@ else
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echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
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endif
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$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " defines: ['NTC']" >> $@
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@@ -195,7 +195,7 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_comm
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POWER_CONF = $(OBJ_DIR)/power-inputs.yml
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include $(vlsi_dir)/power.mk
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$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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echo "power.inputs:" > $@
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echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
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