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Connected UART nicely

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This commit is contained in:
abejgonzalez
2020-09-11 16:55:25 -07:00
parent 56eead4053
commit e98a0f172f
5 changed files with 11 additions and 91 deletions
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2
fpga/Makefile
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@@ -26,7 +26,7 @@ CONFIG := FakeBringupConfig
CONFIG_PACKAGE := chipyard.fpga.vcu118
GENERATOR_PACKAGE := chipyard
TB := none # unused
TOP := ChipTop
TOP := VCU118Platform
# setup the board to use
BOARD ?= arty

6
fpga/src/main/scala/vcu118/Configs.scala
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@@ -21,8 +21,7 @@ import sifive.fpgashells.shell.{DesignKey}
import chipyard.{BuildTop}
class WithChipyardBuildTop extends Config((site, here, up) => {
//case DesignKey => { (p:Parameters) => p(BuildTop)(p) }
case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) }
case DesignKey => {(p: Parameters) => new VCU118Platform()(p) }
})
class WithBringupUARTs extends Config((site, here, up) => {
@@ -32,7 +31,6 @@ class WithBringupUARTs extends Config((site, here, up) => {
})
class FakeBringupConfig extends Config(
new WithUARTConnection1 ++
new WithBringupUARTs ++
new WithChipyardBuildTop ++
new chipyard.config.WithBootROM ++
@@ -47,5 +45,5 @@ class FakeBringupConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

69
fpga/src/main/scala/vcu118/IOBinders.scala
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@@ -1,69 +0,0 @@
package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{attach, IO}
import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.subsystem.{NExtTopInterrupts}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.mockaon._
import sifive.blocks.devices.jtag._
import sifive.blocks.devices.pinctrl._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
import chipsalliance.rocketchip.config._
import sifive.fpgashells.shell._
import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters}
import chipyard.{HasHarnessSignalReferences}
import freechips.rocketchip.diplomacy._
class WithUARTConnection1 extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
implicit val p: Parameters = GetSystemParameters(system)
val io_uart_pins = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") }
(io_uart_pins zip system.uart) map { case (p, r) => p <> r }
val harnessFn = (th: HasHarnessSignalReferences) => {
println(th)
println("Got here - -- - - - ")
Nil
}
//val harnessFn = (baseTh: HasHarnessSignalReferences) => {
// println("DEBUG: ---------------------- 0")
// baseTh match { case th: VCU118Shell =>
// println("DEBUG: ---------------------- 1")
// val io_uart_pins_bb = p(PeripheryUARTKey) map { c => BundleBridgeSource(() => (new UARTPortIO(c))) }
// InModuleBody {
// (io_uart_pins_bb zip io_uart_pins) map { case (p, r) => p.bundle <> r }
// }
// require(p(PeripheryUARTKey).size >= 1)
// println("DEBUG: ---------------------- 2")
// th.designParameters(UARTOverlayKey).foreach { uok =>
// println("DEBUG: ---------------------- 3")
// uok.place(UARTDesignInput(io_uart_pins_bb(0))).overlayOutput
// }
// Nil
// }
//}
Seq((Nil, Nil, Some(harnessFn)))
}
})

0
fpga/src/main/scala/vcu118/Shell.scala
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25
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -5,32 +5,23 @@ import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp}
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.diplomacy.{InModuleBody}
import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell._
import sifive.fpgashells.clocks._
import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
import sifive.blocks.devices.uart._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell with HasHarnessSignalReferences {
val pllResetAsReset = InModuleBody{ Wire(Reset()) }
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell {
InModuleBody {
pllResetAsReset := pllReset
}
require(p(PeripheryUARTKey).size >= 1)
lazy val harnessClock = this.module.sysclk
lazy val harnessReset = pllResetAsReset.getWrappedValue
val success = false.B
lazy val dutReset = pllResetAsReset.getWrappedValue
// must be after HasHarnessSignalReferences assignments
println(s"DEBUG: ----- sz:${topDesign.harnessFunctions.size}")
topDesign match { case d: HasTestHarnessFunctions =>
println(s"DEBUG: ----- sz:${d.harnessFunctions.size}")
d.harnessFunctions.foreach(_(this))
designParameters(UARTOverlayKey).foreach { uok =>
topDesign match { case td: HasPlatformIO =>
io_uart_bb))
}
}
}