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Connected UART nicely

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This commit is contained in:
abejgonzalez
2020-09-11 16:55:25 -07:00
parent 56eead4053
commit e98a0f172f
5 changed files with 11 additions and 91 deletions
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6
fpga/src/main/scala/vcu118/Configs.scala
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@@ -21,8 +21,7 @@ import sifive.fpgashells.shell.{DesignKey}
import chipyard.{BuildTop}
class WithChipyardBuildTop extends Config((site, here, up) => {
//case DesignKey => { (p:Parameters) => p(BuildTop)(p) }
case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) }
case DesignKey => {(p: Parameters) => new VCU118Platform()(p) }
})
class WithBringupUARTs extends Config((site, here, up) => {
@@ -32,7 +31,6 @@ class WithBringupUARTs extends Config((site, here, up) => {
})
class FakeBringupConfig extends Config(
new WithUARTConnection1 ++
new WithBringupUARTs ++
new WithChipyardBuildTop ++
new chipyard.config.WithBootROM ++
@@ -47,5 +45,5 @@ class FakeBringupConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)