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Merge pull request #1891 from ucb-bar/name_domains

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Name all the generated ClockDomains
This commit is contained in:
Jerry Zhao
2024-05-30 16:05:16 -07:00
committed by GitHub
parent 77972c8715 2d2abed586
commit eb6910aae0
4 changed files with 5 additions and 4 deletions
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3
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -37,7 +37,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar

2
generators/rocket-chip

Submodule generators/rocket-chip updated: a235684242...3cec0f0dee

2
generators/rocket-chip-blocks

Submodule generators/rocket-chip-blocks updated: 2fc961f356...c667be9bb3

2
generators/testchipip

Submodule generators/testchipip updated: 104df6a81f...7a30dc737d