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Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem

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abejgonzalez
2020-11-23 16:58:34 -08:00
parent 8f6de22e72
commit f1fdab5bd3
3 changed files with 10 additions and 6 deletions
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7
fpga/src/main/scala/vcu118/Configs.scala
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@@ -39,11 +39,6 @@ class WithSystemModifications extends Config((site, here, up) => {
case SerialTLKey => None // remove serialized tl port
})
class WithTLBackingMemory extends Config((site, here, up) => {
case ExtMem => None // disable AXI backing memory
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})
// DOC include start: AbstractVCU118 and Rocket
class WithVCU118Tweaks extends Config(
new WithUART ++
@@ -53,7 +48,7 @@ class WithVCU118Tweaks extends Config(
new WithSPIIOPassthrough ++
new WithTLIOPassthrough ++
new WithDefaultPeripherals ++
new WithTLBackingMemory ++ // use TL backing memory
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++