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remove crossings in single clock domain

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alonamid
2021-06-02 21:26:29 -07:00
parent abd7bfa607
commit f2b56072a1
1 changed files with 0 additions and 2 deletions
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2
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -109,8 +109,6 @@ class WithFireSimConfigTweaks extends Config(
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz)
new chipyard.config.WithAsynchrousMemoryBusCrossing ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++
new WithFireSimDesignTweaks
)