WIP: Add the ability to generate a hammer-sim config for gate-level sims
Still need to work on the asm-test/benchmark integration
This commit is contained in:
Colin Schmidt
@@ -25,10 +25,7 @@ sim_prefix = simv
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
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sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
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PERMISSIVE_ON=+permissive
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include $(base_dir)/vcs.mk
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PERMISSIVE_OFF=+permissive-off
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WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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.PHONY: default debug
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.PHONY: default debug
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default: $(sim)
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default: $(sim)
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35
vcs.mk
Normal file
35
vcs.mk
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@@ -0,0 +1,35 @@
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PERMISSIVE_ON=+permissive
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PERMISSIVE_OFF=+permissive-off
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WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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VCS_CC_OPTS = \
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-CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-std=c++11"
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VCS_NONCC_OPTS = \
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$(RISCV)/lib/libfesvr.a \
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+lint=all,noVCDE,noONGS,noUI \
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-error=PCWM-L \
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-timescale=1ns/10ps \
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-quiet \
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-q \
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+rad \
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+v2k \
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+vcs+lic+wait \
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+vc+list \
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-f $(sim_common_files) \
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-sverilog \
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+incdir+$(build_dir) \
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$(sim_vsrcs) \
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+libext+.v
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VCS_DEFINE_OPTS = \
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+define+CLOCK_PERIOD=1.0 \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN
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114
vlsi/Makefile
114
vlsi/Makefile
@@ -87,11 +87,123 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
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cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
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cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
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cd $(vlsi_dir) && cp output.json $@
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cd $(vlsi_dir) && cp output.json $@
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#########################################################################################
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# simulation input configuration
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#########################################################################################
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include $(base_dir)/vcs.mk
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SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
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SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
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$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " level: 'gl'" >> $@
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echo " input_files:" >> $@
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for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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echo " timescale: '1ns/10ps'" >> $@
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echo " options: [" >> $@
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echo " '$(RISCV)/lib/libfesvr.a'," >> $@
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echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@
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echo " '-error=PCWM-L'," >> $@
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echo " '-quiet'," >> $@
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echo " '-q'," >> $@
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echo " '+rad'," >> $@
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echo " '+v2k'," >> $@
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echo " '+vcs+lic+wait'," >> $@
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echo " '+vc+list'," >> $@
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echo " '-f $(sim_common_files)'," >> $@
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echo " '-sverilog']" >> $@
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echo " options_meta: 'append'" >> $@
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echo " defines: [" >> $@
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echo " 'CLOCK_PERIOD=1.0'," >> $@
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echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@
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echo " 'STOP_COND=!$(TB).reset'," >> $@
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echo " 'RANDOMIZE_MEM_INIT'," >> $@
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echo " 'RANDOMIZE_REG_INIT'," >> $@
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echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@
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echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@
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echo " defines_meta: 'append'" >> $@
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echo " compiler_opts: [" >> $@
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echo " '-I$(RISCV)/include'," >> $@
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echo " '-std=c++11']" >> $@
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echo " compiler_opts_meta: 'append'" >> $@
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echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
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echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
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echo " execution_flags: [" >> $@
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echo " '+max-cycles=$(timeout_cycles)'," >> $@
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for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \
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echo ' "'$$x'",' >> $@; \
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done
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echo " ]" >> $@
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echo " execution_flags_meta: 'append'" >> $@
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echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@
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$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " level: 'gl'" >> $@
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echo " input_files:" >> $@
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for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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echo " timescale: '1ns/10ps'" >> $@
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echo " options: [" >> $@
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echo " '$(RISCV)/lib/libfesvr.a'," >> $@
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echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@
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echo " '-error=PCWM-L'," >> $@
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echo " '-quiet'," >> $@
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echo " '-q'," >> $@
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echo " '+rad'," >> $@
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echo " '+v2k'," >> $@
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echo " '+vcs+lic+wait'," >> $@
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echo " '+vc+list'," >> $@
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echo " '-f $(sim_common_files)'," >> $@
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echo " '-sverilog'," >> $@
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echo " '-debug_pp']" >> $@
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echo " options_meta: 'append'" >> $@
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echo " defines: [" >> $@
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echo " 'DEBUG'," >> $@
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echo " 'CLOCK_PERIOD=1.0'," >> $@
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echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@
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echo " 'STOP_COND=!$(TB).reset'," >> $@
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echo " 'RANDOMIZE_MEM_INIT'," >> $@
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echo " 'RANDOMIZE_REG_INIT'," >> $@
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echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@
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echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@
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echo " defines_meta: 'append'" >> $@
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echo " compiler_opts: [" >> $@
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echo " '-I$(RISCV)/include'," >> $@
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echo " '-std=c++11']" >> $@
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echo " compiler_opts_meta: 'append'" >> $@
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echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
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echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
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echo " execution_flags: [" >> $@
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echo " '+max-cycles=$(timeout_cycles)'," >> $@
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for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \
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echo ' "'$$x'",' >> $@; \
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done
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echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@
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echo " execution_flags_meta: 'append'" >> $@
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echo " tb_dut: 'testHarness.top'" >> $@
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echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@
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#echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@
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$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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echo "power.inputs:" > $@
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sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF)
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#########################################################################################
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#########################################################################################
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# synthesis input configuration
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# synthesis input configuration
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#########################################################################################
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#########################################################################################
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SYN_CONF = $(OBJ_DIR)/inputs.yml
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SYN_CONF = $(OBJ_DIR)/inputs.yml
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GENERATED_CONFS = $(SYN_CONF)
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GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF)
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ifeq ($(CUSTOM_VLOG), )
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ifeq ($(CUSTOM_VLOG), )
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GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
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GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
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endif
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endif
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