Combine generates, make it a trait (#11)
* [stevo]: combine generates, make it a trait * [stevo]: add Generator ala rocket-chip, some other cleanup * [stevo]: remove Generator, since that generates firrtl... * [stevo]: still debugging * [stevo]: okay i think it works now * [stevo]: oops * Refactor new generate code. Mostly just style stuff.
This commit is contained in:
Stevo
217
tapeout/src/main/scala/transforms/Generate.scala
Normal file
217
tapeout/src/main/scala/transforms/Generate.scala
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@@ -0,0 +1,217 @@
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.ir._
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import firrtl.annotations._
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import firrtl.passes.Pass
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import java.io.File
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import firrtl.annotations.AnnotationYamlProtocol._
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import net.jcazevedo.moultingyaml._
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import com.typesafe.scalalogging.LazyLogging
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object AllModules {
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private var modules = Set[String]()
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def add(module: String) = {
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modules = modules | Set(module)
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}
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def rename(module: String) = {
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var new_name = module
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while (modules.contains(new_name))
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new_name = new_name + "_inTestHarness"
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new_name
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}
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}
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case class ParsedInput(args: Seq[String]) extends LazyLogging {
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var input: Option[String] = None
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var output: Option[String] = None
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var topOutput: Option[String] = None
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var harnessOutput: Option[String] = None
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var annoFile: Option[String] = None
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var synTop: Option[String] = None
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var harnessTop: Option[String] = None
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var seqMemFlags: Option[String] = Some("-o:unused.confg")
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var listClocks: Option[String] = Some("-o:unused.clocks")
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var usedOptions = Set.empty[Integer]
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args.zipWithIndex.foreach{ case (arg, i) =>
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arg match {
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case "-i" => {
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input = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "-o" => {
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output = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--top-o" => {
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topOutput = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--harness-o" => {
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harnessOutput = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--anno-file" => {
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annoFile = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--syn-top" => {
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synTop = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--harness-top" => {
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harnessTop = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--seq-mem-flags" => {
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seqMemFlags = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--list-clocks" => {
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listClocks = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case _ => {
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if (! (usedOptions contains i)) {
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logger.error("Unknown option " + arg)
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}
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}
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}
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}
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}
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// Requires two phases, one to collect modules below synTop in the hierarchy
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// and a second to remove those modules to generate the test harness
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sealed trait GenerateTopAndHarnessApp extends App with LazyLogging {
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lazy val options: ParsedInput = ParsedInput(args)
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lazy val input = options.input
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lazy val output = options.output
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lazy val topOutput = options.topOutput
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lazy val harnessOutput = options.harnessOutput
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lazy val annoFile = options.annoFile
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lazy val synTop = options.synTop
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lazy val harnessTop = options.harnessTop
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lazy val seqMemFlags = options.seqMemFlags
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lazy val listClocks = options.listClocks
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private def getFirstPhasePasses(top: Boolean, harness: Boolean): Seq[Transform] = {
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val pre = Seq(
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new ReParentCircuit(synTop.get),
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new RemoveUnusedModules
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)
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val enumerate = if (harness) { Seq(
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new EnumerateModules( { m => if (m.name != options.synTop.get) { AllModules.add(m.name) } } )
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) } else Seq()
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val post = if (top) { Seq(
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new passes.memlib.InferReadWrite(),
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new passes.memlib.ReplSeqMem(),
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new passes.clocklist.ClockListTransform()
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) } else Seq()
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pre ++ enumerate ++ post
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}
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private def getFirstPhaseAnnotations(top: Boolean): AnnotationMap = {
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if (top) {
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//Load annotations from file
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val annotationArray = annoFile match {
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case None => Array[Annotation]()
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case Some(fileName) => {
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val annotations = new File(fileName)
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if(annotations.exists) {
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val annotationsYaml = io.Source.fromFile(annotations).getLines().mkString("\n").parseYaml
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annotationsYaml.convertTo[Array[Annotation]]
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} else {
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Array[Annotation]()
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}
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}
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}
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// add new annotations
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AnnotationMap(Seq(
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passes.memlib.InferReadWriteAnnotation(
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s"${synTop.get}"
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),
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passes.clocklist.ClockListAnnotation(
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s"-c:${synTop.get}:-m:${synTop.get}:${listClocks.get}"
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),
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passes.memlib.ReplSeqMemAnnotation(
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s"-c:${synTop.get}:${seqMemFlags.get}"
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)
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) ++ annotationArray)
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} else { AnnotationMap(Seq.empty) }
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}
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private def getSecondPhasePasses: Seq[Transform] = {
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// always the same for now
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Seq(
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new ConvertToExtMod((m) => m.name == synTop.get),
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new RemoveUnusedModules,
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new RenameModulesAndInstances((m) => AllModules.rename(m))
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)
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}
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// always the same for now
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private def getSecondPhaseAnnotations: AnnotationMap = AnnotationMap(Seq.empty)
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// Top Generation
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protected def firstPhase(top: Boolean, harness: Boolean): Unit = {
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require(top || harness, "Must specify either top or harness")
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firrtl.Driver.compile(
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input.get,
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topOutput.getOrElse(output.get),
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new VerilogCompiler(),
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Parser.UseInfo,
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getFirstPhasePasses(top, harness),
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getFirstPhaseAnnotations(top)
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)
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}
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// Harness Generation
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protected def secondPhase: Unit = {
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firrtl.Driver.compile(
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input.get,
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harnessOutput.getOrElse(output.get),
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new VerilogCompiler(),
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Parser.UseInfo,
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getSecondPhasePasses,
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getSecondPhaseAnnotations
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)
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}
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}
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object GenerateTop extends GenerateTopAndHarnessApp {
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// warn about unused options
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harnessOutput.foreach(n => logger.warn(s"Not using harness output filename $n since you asked for just a top-level output."))
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topOutput.foreach(_.foreach{
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n => logger.warn(s"Not using generic output filename $n since you asked for just a top-level output and also specified a generic output.")})
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// Only need a single phase to generate the top module
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firstPhase(top = true, harness = false)
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}
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object GenerateHarness extends GenerateTopAndHarnessApp {
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// warn about unused options
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topOutput.foreach(n => logger.warn(s"Not using top-level output filename $n since you asked for just a test harness."))
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annoFile.foreach(n => logger.warn(s"Not using annotations file $n since you asked for just a test harness."))
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seqMemFlags.filter(_ != "-o:unused.confg").foreach {
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n => logger.warn(s"Not using SeqMem flags $n since you asked for just a test harness.") }
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listClocks.filter(_ != "-o:unused.clocks").foreach {
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n => logger.warn(s"Not using clocks list $n since you asked for just a test harness.") }
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harnessOutput.foreach(_.foreach{
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n => logger.warn(s"Not using generic output filename $n since you asked for just a test harness and also specified a generic output.")})
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// Do minimal work for the first phase to generate test harness
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firstPhase(top = false, harness = true)
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secondPhase
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}
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object GenerateTopAndHarness extends GenerateTopAndHarnessApp {
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// warn about unused options
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output.foreach(n => logger.warn(s"Not using generic output filename $n since you asked for both a top-level output and a test harness."))
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// Do everything, top and harness generation
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firstPhase(top = true, harness = true)
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secondPhase
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}
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@@ -1,79 +0,0 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.ir._
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import firrtl.annotations._
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import firrtl.passes.Pass
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object AllModules {
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private var modules = Set[String]()
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def add(module: String) = {
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modules = modules | Set(module)
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}
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def rename(module: String) = {
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var new_name = module
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while (modules.contains(new_name))
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new_name = new_name + "_inTestHarness"
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new_name
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}
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}
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object GenerateHarness extends App {
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var input: Option[String] = None
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var output: Option[String] = None
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var synTop: Option[String] = None
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var harnessTop: Option[String] = None
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var usedOptions = Set.empty[Integer]
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args.zipWithIndex.foreach{ case (arg, i) =>
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arg match {
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case "-i" => {
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input = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "-o" => {
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output = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--syn-top" => {
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synTop = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--harness-top" => {
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harnessTop = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case _ => {
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if (! (usedOptions contains i)) {
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error("Unknown option " + arg)
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}
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}
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}
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}
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firrtl.Driver.compile(
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input.get,
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output.get,
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new VerilogCompiler(),
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Parser.UseInfo,
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Seq(
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new ReParentCircuit(synTop.get),
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new RemoveUnusedModules,
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new EnumerateModules( { m => if (m.name != synTop.get) { AllModules.add(m.name) } } )
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)
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)
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firrtl.Driver.compile(
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input.get,
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output.get,
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new VerilogCompiler(),
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Parser.UseInfo,
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Seq(
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new ConvertToExtMod((m) => m.name == synTop.get),
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new RemoveUnusedModules,
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new RenameModulesAndInstances((m) => AllModules.rename(m))
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)
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)
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}
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@@ -1,77 +0,0 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.ir._
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import firrtl.annotations._
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import firrtl.passes.Pass
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object GenerateTop extends App {
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var input: Option[String] = None
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var output: Option[String] = None
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var synTop: Option[String] = None
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var harnessTop: Option[String] = None
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var seqMemFlags: Option[String] = Some("-o:unused.confg")
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var listClocks: Option[String] = Some("-o:unused.clocks")
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var usedOptions = Set.empty[Integer]
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args.zipWithIndex.foreach{ case (arg, i) =>
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arg match {
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case "-i" => {
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input = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "-o" => {
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output = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--syn-top" => {
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synTop = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--harness-top" => {
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harnessTop = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--seq-mem-flags" => {
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seqMemFlags = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case "--list-clocks" => {
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listClocks = Some(args(i+1))
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usedOptions = usedOptions | Set(i+1)
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}
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case _ => {
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if (! (usedOptions contains i)) {
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error("Unknown option " + arg)
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}
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}
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}
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}
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firrtl.Driver.compile(
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input.get,
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output.get,
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new VerilogCompiler(),
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Parser.UseInfo,
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Seq(
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new ReParentCircuit(synTop.get),
|
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new RemoveUnusedModules,
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new passes.memlib.InferReadWrite(),
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new passes.memlib.ReplSeqMem(),
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new passes.clocklist.ClockListTransform()
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),
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AnnotationMap(Seq(
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passes.memlib.InferReadWriteAnnotation(
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s"${synTop.get}"
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),
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passes.clocklist.ClockListAnnotation(
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s"-c:${synTop.get}:-m:${synTop.get}:${listClocks.get}"
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),
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passes.memlib.ReplSeqMemAnnotation(
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s"-c:${synTop.get}:${seqMemFlags.get}"
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)
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))
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)
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}
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@@ -1,120 +0,0 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.ir._
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import firrtl.annotations._
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import firrtl.passes.Pass
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import java.io.File
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import firrtl.annotations.AnnotationYamlProtocol._
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import net.jcazevedo.moultingyaml._
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|
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object GenerateTopAndHarness extends App {
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var input: Option[String] = None
|
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var topOutput: Option[String] = None
|
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var harnessOutput: Option[String] = None
|
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var annoFile: Option[String] = None
|
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var synTop: Option[String] = None
|
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var harnessTop: Option[String] = None
|
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var seqMemFlags: Option[String] = Some("-o:unused.confg")
|
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var listClocks: Option[String] = Some("-o:unused.clocks")
|
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|
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var usedOptions = Set.empty[Integer]
|
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args.zipWithIndex.foreach{ case (arg, i) =>
|
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arg match {
|
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case "-i" => {
|
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input = Some(args(i+1))
|
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usedOptions = usedOptions | Set(i+1)
|
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}
|
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case "--top-o" => {
|
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topOutput = Some(args(i+1))
|
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usedOptions = usedOptions | Set(i+1)
|
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}
|
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case "--harness-o" => {
|
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harnessOutput = Some(args(i+1))
|
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usedOptions = usedOptions | Set(i+1)
|
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}
|
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case "--anno-file" => {
|
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annoFile = Some(args(i+1))
|
||||
usedOptions = usedOptions | Set(i+1)
|
||||
}
|
||||
case "--syn-top" => {
|
||||
synTop = Some(args(i+1))
|
||||
usedOptions = usedOptions | Set(i+1)
|
||||
}
|
||||
case "--harness-top" => {
|
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harnessTop = Some(args(i+1))
|
||||
usedOptions = usedOptions | Set(i+1)
|
||||
}
|
||||
case "--seq-mem-flags" => {
|
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seqMemFlags = Some(args(i+1))
|
||||
usedOptions = usedOptions | Set(i+1)
|
||||
}
|
||||
case "--list-clocks" => {
|
||||
listClocks = Some(args(i+1))
|
||||
usedOptions = usedOptions | Set(i+1)
|
||||
}
|
||||
case _ => {
|
||||
if (! (usedOptions contains i)) {
|
||||
error("Unknown option " + arg)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
//Load annotations from file
|
||||
val annotationArray = annoFile match {
|
||||
case None => Array[Annotation]()
|
||||
case Some(fileName) => {
|
||||
val annotations = new File(fileName)
|
||||
if(annotations.exists) {
|
||||
val annotationsYaml = io.Source.fromFile(annotations).getLines().mkString("\n").parseYaml
|
||||
annotationsYaml.convertTo[Array[Annotation]]
|
||||
} else {
|
||||
Array[Annotation]()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//Top Generation
|
||||
firrtl.Driver.compile(
|
||||
input.get,
|
||||
topOutput.get,
|
||||
new VerilogCompiler(),
|
||||
Parser.UseInfo,
|
||||
Seq(
|
||||
new ReParentCircuit(synTop.get),
|
||||
new RemoveUnusedModules,
|
||||
new EnumerateModules( { m => if (m.name != synTop.get) { AllModules.add(m.name) } } ),
|
||||
new passes.memlib.InferReadWrite(),
|
||||
new passes.memlib.ReplSeqMem(),
|
||||
new passes.clocklist.ClockListTransform()
|
||||
),
|
||||
AnnotationMap(Seq(
|
||||
passes.memlib.InferReadWriteAnnotation(
|
||||
s"${synTop.get}"
|
||||
),
|
||||
passes.clocklist.ClockListAnnotation(
|
||||
s"-c:${synTop.get}:-m:${synTop.get}:${listClocks.get}"
|
||||
),
|
||||
passes.memlib.ReplSeqMemAnnotation(
|
||||
s"-c:${synTop.get}:${seqMemFlags.get}"
|
||||
)
|
||||
) ++ annotationArray)
|
||||
)
|
||||
|
||||
//Harness Generation
|
||||
firrtl.Driver.compile(
|
||||
input.get,
|
||||
harnessOutput.get,
|
||||
new VerilogCompiler(),
|
||||
Parser.UseInfo,
|
||||
Seq(
|
||||
new ConvertToExtMod((m) => m.name == synTop.get),
|
||||
new RemoveUnusedModules,
|
||||
new RenameModulesAndInstances((m) => AllModules.rename(m))
|
||||
)
|
||||
)
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user