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Merge remote-tracking branch 'origin/dev' into HEAD

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This commit is contained in:
Paul Rigge
2020-05-23 22:49:51 +00:00
parent 0cc643bfdb c2c9bc83de
commit f56e367d59
101 changed files with 8537 additions and 708 deletions
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2
generators/ariane

Submodule generators/ariane updated: e02436d2aa...d914fc8f03

2
generators/boom

Submodule generators/boom updated: a26504f34d...f0caca8d6b

95
generators/chipyard/src/main/scala/ChipTop.scala
View File

@@ -12,7 +12,42 @@ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple}
import barstools.iocell.chisel._
case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module))
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p)))
/**
* Chipyard provides three baseline, top-level reset schemes, set using the
* [[GlobalResetSchemeKey]] in a Parameters instance. These are:
*
* 1) Synchronous: The input coming to the chip is synchronous to the provided
* clocks and will be used without modification as a synchronous reset.
* This is safe only for use in FireSim and SW simulation.
*
* 2) Asynchronous: The input reset is asynchronous to the input clock, but it
* is caught and synchronized to that clock before it is dissemenated.
* Thus, downsteam modules will be emitted with synchronously reset state
* elements.
*
* 3) Asynchronous Full: The input reset is asynchronous to the input clock,
* and is used globally as an async reset. Downstream modules will be emitted
* with asynchronously reset state elements.
*
*/
sealed trait GlobalResetScheme {
def pinIsAsync: Boolean
}
sealed trait HasAsyncInput { self: GlobalResetScheme =>
def pinIsAsync = true
}
sealed trait HasSyncInput { self: GlobalResetScheme =>
def pinIsAsync = false
}
case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput
case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput
case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput
case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous)
/**
* The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
@@ -26,16 +61,21 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
// A list of functions to call in the test harness
val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction]
// The system clock
// These are given so that IOCell can use DataMirror and generate ports with
// the right flow (Input/Output)
val systemClock = Wire(Input(Clock()))
// The system reset (synchronous to clock)
val systemReset = Wire(Input(Bool()))
val systemReset = Wire(Input(Reset()))
// The system module specified by BuildSystem
val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) }
val lSystem = p(BuildSystem)(p).suggestName("system")
val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) }
// Call all of the IOBinders and provide them with a default clock and reset
withClockAndReset(systemClock, systemReset) {
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3
// Call each IOBinder on both the lazyModule instance and the module
// instance. Generally, an IOBinder PF should only be defined on one, so
// this should not lead to two invocations.
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3
// We ignore _ports for now...
iocells ++= _iocells.flatten
harnessFunctions ++= _harnessFunctions.flatten
@@ -45,13 +85,22 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
/**
* A simple clock and reset implementation that punches out clock and reset ports with the same
* names as the implicit clock and reset for standard Module classes. Reset is synchronous to
* clock, which may not be a good idea to use for tapeouts.
* names as the implicit clock and reset for standard Module classes. Three basic reset schemes
* are provided. See [[GlobalResetScheme]].
*/
trait HasChipTopSimpleClockAndReset { this: BaseChipTop =>
val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock"))
val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"))
val (reset, systemResetIO) = p(GlobalResetSchemeKey) match {
case GlobalResetSynchronous =>
IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"))
case GlobalResetAsynchronousFull =>
IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"), abstractResetAsAsync = true)
case GlobalResetAsynchronous =>
val asyncResetCore = Wire(Input(AsyncReset()))
systemReset := ResetCatchAndSync(systemClock, asyncResetCore.asBool)
IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_reset"), abstractResetAsAsync = true)
}
iocells ++= systemClockIO
iocells ++= systemResetIO
@@ -68,35 +117,5 @@ trait HasChipTopSimpleClockAndReset { this: BaseChipTop =>
}
/**
* Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset
* can be asynchronous with clock, which is useful for tapeout configs.
*/
trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop =>
val asyncResetCore = Wire(Input(Bool()))
systemReset := ResetCatchAndSync(systemClock, asyncResetCore)
val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock"))
val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset"))
iocells ++= systemClockIO
iocells ++= asyncResetIO
// Add a TestHarnessFunction that connects clock and areset
harnessFunctions += { (th: TestHarness) => {
// Connect clock; it's not done implicitly with RawModule
clock := th.clock
// Connect reset; it's not done implicitly with RawModule
// Note that we need to use dutReset, not harnessReset
areset := th.dutReset
Nil
} }
}
class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p)
with HasChipTopSimpleClockAndReset
class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p)
with HasChipTopSimpleClockAndCaughtReset

32
generators/chipyard/src/main/scala/ConfigFragments.scala
View File

@@ -13,15 +13,16 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
import freechips.rocketchip.util.{AsyncResetReg}
import boom.common.{BoomTilesKey}
import ariane.{ArianeTilesKey}
import testchipip._
import hwacha.{Hwacha}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset}
import chipyard.{BuildTop, BuildSystem}
/**
* TODO: Why do we need this?
@@ -52,8 +53,10 @@ class WithUART extends Config((site, here, up) => {
UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
})
class WithNoGPIO extends Config((site, here, up) => {
case PeripheryGPIOKey => Seq()
class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
// Note: the default size matches freedom with the addresses below
case PeripherySPIFlashKey => Seq(
SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size))
})
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -66,10 +69,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
})
class WithTracegenSystem extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module)
case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p))
})
class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) =>
r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length))
@@ -80,12 +82,6 @@ class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here
case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size)
})
// ------------------
// Multi-RoCC Support
// ------------------
/**
* Map from a hartId to a particular RoCC accelerator
*/
@@ -151,12 +147,8 @@ class WithControlCore extends Config((site, here, up) => {
case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
})
/**
* Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to
* the top-level reset, allowing it to be asynchronous with the clock.
* NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config
*/
class WithChipTopCaughtReset extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top"))
class WithTraceIO extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
})

3
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -19,11 +19,13 @@ class DigitalTop(implicit p: Parameters) extends System
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget
with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{
override lazy val module = new DigitalTopModule(this)
}
@@ -34,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
with testchipip.CanHavePeripherySerialModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with icenet.CanHavePeripheryIceNICModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with freechips.rocketchip.util.DontTouch

40
generators/chipyard/src/main/scala/Generator.scala
View File

@@ -1,40 +1,6 @@
package chipyard
import scala.util.Try
import firrtl.options.{StageMain}
import chipyard.stage.ChipyardStage
import chisel3._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.system.{TestGeneration}
object Generator extends GeneratorApp {
// add unique test suites
override def addTestSuites {
implicit val p: Parameters = params
TestSuiteHelper.addRocketTestSuites
TestSuiteHelper.addBoomTestSuites
TestSuiteHelper.addArianeTestSuites
// if hwacha parameter exists then generate its tests
// TODO: find a more elegant way to do this. either through
// trying to disambiguate BuildRoCC, having a AccelParamsKey,
// or having the Accelerator/Tile add its own tests
import hwacha.HwachaTestSuites._
if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
TestGeneration.addSuites(rv64uv.map(_("p")))
TestGeneration.addSuites(rv64uv.map(_("vp")))
TestGeneration.addSuite(rv64sv("p"))
TestGeneration.addSuite(hwachaBmarks)
}
}
// specify the name that the generator outputs files as
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
// generate files
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}
object Generator extends StageMain(new ChipyardStage)

129
generators/chipyard/src/main/scala/IOBinders.scala
View File

@@ -8,10 +8,12 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.util._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import barstools.iocell.chisel._
@@ -87,10 +89,8 @@ object AddIOCells {
def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = {
gpios.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val g = IO(Analog(1.W))
g.suggestName("gpio_${i}_${j}")
val iocell = genFn()
iocell.suggestName(s"iocell_gpio_${i}_${j}")
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = genFn().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
@@ -103,7 +103,7 @@ object AddIOCells {
/**
* Add IO cells to a SiFive UART devices and name the IO ports.
* @param gpios A Seq of UART port bundles
* @param uartPins A Seq of UART port bundles
* @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references)
*/
def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = {
@@ -114,20 +114,62 @@ object AddIOCells {
}).unzip
}
/**
* Add IO cells to a SiFive SPI devices and name the IO ports.
* @param spiPins A Seq of SPI port bundles
* @param basename The base name for this port (defaults to "spi")
* @param genFn A callable function to generate a DigitalGPIOCell module to use
* @return Returns a tuple of (A Seq of top-level SPIChipIO IOs; a 2D Seq of IOCell module references)
*/
def spi(spiPins: Seq[SPIPortIO], basename: String = "spi", genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[SPIChipIO], Seq[Seq[IOCell]]) = {
spiPins.zipWithIndex.map({ case (s, i) =>
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"${basename}_${i}")
val iocellBase = s"iocell_${basename}_${i}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"))
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"))
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = genFn().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
pin.i := iocell.io.i
iocell.io.pad <> ana
iocell
}
(port, dqIOs ++ csIOs ++ sckIOs)
}).unzip
}
/**
* Add IO cells to a debug module and name the IO ports.
* @param gpios A PSDIO bundle
* @param psd A PSDIO bundle
* @param resetctrlOpt An optional ResetCtrlIO bundle
* @param debugOpt An optional DebugIO bundle
* @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references)
*/
def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = {
val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd"))
val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug")))
val debugPortOpt: Option[DebugIO] = optTuple.map(_._1)
val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten
def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters):
(PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = {
val (psdPort, psdIOs) = IOCell.generateIOFromSignal(
psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
val debugTuple = debugOpt.map(d =>
IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1)
val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten
debugPortOpt.foreach(_.suggestName("debug"))
val resetctrlTuple = resetctrlOpt.map(d =>
IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1)
val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten
resetctrlPortOpt.foreach(_.suggestName("resetctrl"))
psdPort.suggestName("psd")
(psdPort, debugPortOpt, psdIOs ++ debugIOs)
(psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs)
}
/**
@@ -160,6 +202,14 @@ class WithUARTAdapter extends OverrideIOBinder({
}
})
class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({
(system: HasPeripherySPIFlashModuleImp) => {
val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi")
val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil }
Seq((ports, ioCells2d.flatten, Some(harnessFn)))
}
})
class WithSimBlockDevice extends OverrideIOBinder({
(system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil
})
@@ -176,29 +226,32 @@ class WithSimNIC extends OverrideIOBinder({
(system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
})
// Note: The parameters instance is accessible only through the BaseSubsystem
// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
// accessible to the IOBinder
// DOC include start: WithSimAXIMem
class WithSimAXIMem extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil
})
// DOC include end: WithSimAXIMem
class WithBlackBoxSimMem extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => {
(system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) =>
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
(system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) =>
val memSize = system.p(ExtMem).get.master.size
val lineSize = system.p(CacheBlockBytes)
(io zip node.in).foreach { case (axi4, (_, edge)) =>
val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
mem.io.axi <> axi4
mem.io.clock := system.clock
mem.io.reset := system.reset
}
}; Nil
val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
mem.io.axi <> io
mem.io.clock := system.module.clock
mem.io.reset := system.module.reset
}
Nil
}
})
class WithSimAXIMMIO extends OverrideIOBinder({
(system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil
(system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil
})
class WithDontTouchPorts extends OverrideIOBinder({
@@ -215,7 +268,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({
})
class WithTieOffL2FBusAXI extends OverrideIOBinder({
(system: CanHaveSlaveAXI4PortModuleImp) => {
(system: CanHaveSlaveAXI4Port with BaseSubsystem) => {
system.l2_frontend_bus_axi4.foreach(axi => {
axi.tieoff()
experimental.DataMirror.directionOf(axi.ar.ready) match {
@@ -235,23 +288,29 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({
class WithTiedOffDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug)
val (psdPort, resetctrlOpt, debugPortOpt, ioCells) =
AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
val harnessFn = (th: chipyard.TestHarness) => {
Debug.tieoffDebug(debugPortOpt, psdPort)
Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p)
// tieoffDebug doesn't actually tie everything off :/
debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
debugPortOpt.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.clock })
d.dmactiveAck := DontCare
d.clock := th.clock
}
Nil
}
Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn)))
Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn)))
}
})
class WithSimDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug)
val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) =
AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
val harnessFn = (th: chipyard.TestHarness) => {
val dtm_success = Wire(Bool())
Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p)
Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p)
when (dtm_success) { th.success := true.B }
th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B)
Nil
@@ -292,4 +351,12 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({
}
})
}
class WithSimDromajoBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp) => {
system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
Nil
}
})
} /* end package object */

22
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -24,6 +24,8 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
import testchipip.{DromajoHelper}
trait HasChipyardTiles extends HasTiles
with CanHavePeripheryPLIC
with CanHavePeripheryCLINT
@@ -52,26 +54,20 @@ trait HasChipyardTiles extends HasTiles
// TODO: investigate why
val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
case (param, crossing) => {
val (tile, rocketLogicalTree) = param match {
val tile = param match {
case r: RocketTileParams => {
val t = LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
(t, t.rocketLogicalTree)
LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
}
case b: BoomTileParams => {
val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
(t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
}
case a: ArianeTileParams => {
val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
(t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
}
}
connectMasterPortsToSBus(tile, crossing)
connectSlavePortsToCBus(tile, crossing)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree)
connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
tile
@@ -110,4 +106,8 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule
// create file with boom params
ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
// Generate C header with relevant information for Dromajo
// This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts
}

4
generators/chipyard/src/main/scala/System.scala
View File

@@ -22,7 +22,6 @@ import freechips.rocketchip.util.{DontTouch}
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class System(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort
@@ -38,8 +37,5 @@ class System(implicit p: Parameters) extends Subsystem
class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MMIOPortModuleImp
with CanHaveSlaveAXI4PortModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

5
generators/chipyard/src/main/scala/TestHarness.scala
View File

@@ -25,9 +25,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
val dut = p(BuildTop)(p)
io.success := false.B
// dutReset can be overridden via a harnessFunction, but by default it is just reset
val dutReset = Wire(Bool())
dutReset := reset
// dutReset assignment can be overridden via a harnessFunction, but by default it is just reset
val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset)
dut.harnessFunctions.foreach(_(this))

83
generators/chipyard/src/main/scala/TestSuites.scala
View File

@@ -5,8 +5,7 @@ import scala.collection.mutable.{LinkedHashSet}
import freechips.rocketchip.subsystem.{RocketTilesKey}
import freechips.rocketchip.tile.{XLen}
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
import boom.common.{BoomTilesKey}
import ariane.{ArianeTilesKey}
@@ -56,10 +55,13 @@ object RegressionTestSuites
/**
* Helper functions to add BOOM or Rocket tests
*/
object TestSuiteHelper
class TestSuiteHelper
{
import freechips.rocketchip.system.DefaultTestSuites._
import RegressionTestSuites._
val suites = collection.mutable.ListMap[String, RocketTestSuite]()
def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }
def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
/**
* Add BOOM tests (asm, bmark, regression)
@@ -72,33 +74,33 @@ object TestSuiteHelper
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
addSuites(env.map(rv32uf))
if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv32ud))
addSuites(env.map(rv32ud))
}
} else if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv64ud))
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuite(rv32udBenchmarks)
addSuites(env.map(rv64ud))
addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
} else {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites(rvu.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
addSuites(rvi.map(_("p")))
addSuites(rvu.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
@@ -113,31 +115,31 @@ object TestSuiteHelper
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
else
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
addSuites(rvi.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
@@ -152,32 +154,31 @@ object TestSuiteHelper
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
else
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
addSuites(rvi.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
}

4
generators/chipyard/src/main/scala/config/ArianeConfigs.scala
View File

@@ -15,7 +15,6 @@ class ArianeConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
@@ -23,6 +22,7 @@ class ArianeConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new ariane.WithNArianeCores(1) ++ // single Ariane core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class dmiArianeConfig extends Config(
@@ -31,7 +31,6 @@ class dmiArianeConfig extends Config(
new chipyard.iobinders.WithSimAXIMem ++
new chipyard.iobinders.WithTiedOffSerial ++
new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
@@ -39,4 +38,5 @@ class dmiArianeConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new ariane.WithNArianeCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

37
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -13,7 +13,6 @@ class SmallBoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
@@ -23,6 +22,7 @@ class SmallBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new boom.common.WithSmallBooms ++ // small boom config
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class MediumBoomConfig extends Config(
@@ -32,7 +32,6 @@ class MediumBoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -42,6 +41,7 @@ class MediumBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMediumBooms ++ // medium boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class LargeBoomConfig extends Config(
@@ -51,7 +51,6 @@ class LargeBoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -61,6 +60,7 @@ class LargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++ // large boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class MegaBoomConfig extends Config(
@@ -70,7 +70,6 @@ class MegaBoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -80,6 +79,7 @@ class MegaBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMegaBooms ++ // mega boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class DualSmallBoomConfig extends Config(
@@ -89,7 +89,6 @@ class DualSmallBoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -99,6 +98,7 @@ class DualSmallBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class SmallRV32BoomConfig extends Config(
@@ -108,7 +108,6 @@ class SmallRV32BoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -120,6 +119,7 @@ class SmallRV32BoomConfig extends Config(
new boom.common.WithBoomRV32 ++ // rv32 (32bit)
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class HwachaLargeBoomConfig extends Config(
@@ -129,7 +129,6 @@ class HwachaLargeBoomConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -140,6 +139,7 @@ class HwachaLargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class LoopbackNICLargeBoomConfig extends Config(
@@ -151,7 +151,6 @@ class LoopbackNICLargeBoomConfig extends Config(
new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback
new testchipip.WithTSI ++
new icenet.WithIceNIC ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -161,5 +160,27 @@ class LoopbackNICLargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class DromajoBoomConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo
new testchipip.WithTSI ++
new chipyard.config.WithTraceIO ++ // enable the traceio
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

14
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -13,7 +13,6 @@ class LargeBoomAndRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
@@ -25,6 +24,7 @@ class LargeBoomAndRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
// DOC include start: BoomAndRocketWithHwacha
@@ -35,7 +35,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -48,6 +47,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: BoomAndRocketWithHwacha
@@ -58,7 +58,6 @@ class DualLargeBoomAndRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -70,6 +69,7 @@ class DualLargeBoomAndRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: DualBoomAndRocketOneHwacha
@@ -81,7 +81,6 @@ class LargeBoomAndHwachaRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
@@ -95,6 +94,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: DualBoomAndRocketOneHwacha
@@ -107,7 +107,6 @@ class LargeBoomAndRV32RocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -120,6 +119,7 @@ class LargeBoomAndRV32RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
@@ -131,7 +131,6 @@ class DualLargeBoomAndDualRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -143,6 +142,7 @@ class DualLargeBoomAndDualRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: DualBoomAndRocket
@@ -153,7 +153,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithControlCore ++ // add small control core to last hartid
@@ -166,5 +165,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

115
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -13,7 +13,6 @@ class RocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
@@ -22,6 +21,7 @@ class RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class HwachaRocketConfig extends Config(
@@ -31,7 +31,6 @@ class HwachaRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -41,6 +40,7 @@ class HwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: GemminiRocketConfig
@@ -51,7 +51,6 @@ class GemminiRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -61,6 +60,7 @@ class GemminiRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GemminiRocketConfig
@@ -71,7 +71,6 @@ class RoccRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -81,6 +80,7 @@ class RoccRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: JtagRocket
@@ -91,7 +91,6 @@ class jtagRocketConfig extends Config(
new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -101,6 +100,7 @@ class jtagRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: JtagRocket
@@ -111,7 +111,6 @@ class dmiRocketConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffSerial ++
new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -120,6 +119,7 @@ class dmiRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: DmiRocket
@@ -131,7 +131,6 @@ class GCDTLRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithUART ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -141,6 +140,7 @@ class GCDTLRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GCDTLRocketConfig
@@ -153,7 +153,6 @@ class GCDAXI4BlackBoxRocketConfig extends Config(
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithUART ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink
@@ -162,9 +161,50 @@ class GCDAXI4BlackBoxRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GCDAXI4BlackBoxRocketConfig
class LargeSPIFlashROMRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new chipyard.iobinders.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class SmallSPIFlashRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new chipyard.iobinders.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable)
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB)
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class SimBlockDeviceRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
@@ -174,7 +214,6 @@ class SimBlockDeviceRocketConfig extends Config(
new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new testchipip.WithTSI ++
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -183,6 +222,7 @@ class SimBlockDeviceRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class BlockDeviceModelRocketConfig extends Config(
@@ -194,7 +234,6 @@ class BlockDeviceModelRocketConfig extends Config(
new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel
new testchipip.WithTSI ++
new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -203,6 +242,7 @@ class BlockDeviceModelRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: GPIORocketConfig
@@ -223,6 +263,7 @@ class GPIORocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GPIORocketConfig
@@ -235,13 +276,13 @@ class QuadRocketConfig extends Config(
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class RV32RocketConfig extends Config(
@@ -251,7 +292,6 @@ class RV32RocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
@@ -260,6 +300,7 @@ class RV32RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class GB1MemoryRocketConfig extends Config(
@@ -269,7 +310,6 @@ class GB1MemoryRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -279,6 +319,7 @@ class GB1MemoryRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: Sha3Rocket
@@ -289,7 +330,6 @@ class Sha3RocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -299,6 +339,7 @@ class Sha3RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: Sha3Rocket
@@ -310,7 +351,6 @@ class InitZeroRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -320,6 +360,7 @@ class InitZeroRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: InitZeroRocketConfig
@@ -332,7 +373,6 @@ class LoopbackNICRocketConfig extends Config(
new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback
new testchipip.WithTSI ++
new icenet.WithIceNIC ++ // add an IceNIC
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -341,6 +381,7 @@ class LoopbackNICRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: scratchpadrocket
@@ -351,7 +392,6 @@ class ScratchpadRocketConfig extends Config(
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new testchipip.WithBackingScratchpad ++ // add backing scratchpad
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -361,6 +401,7 @@ class ScratchpadRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: scratchpadrocket
@@ -372,7 +413,6 @@ class RingSystemBusRocketConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
@@ -382,6 +422,7 @@ class RingSystemBusRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: RingSystemBusRocket
@@ -396,3 +437,41 @@ class UIntTestFIRRocketConfig extends Config (
new RocketConfig
)
// DOC include end: FIRRocketConfig
class SmallNVDLARocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class LargeNVDLARocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

5
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -8,6 +8,7 @@ class TraceGenConfig extends Config(
new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class NonBlockingTraceGenConfig extends Config(
@@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config(
new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class BoomTraceGenConfig extends Config(
@@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config(
new chipyard.config.WithTracegenSystem ++
new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class NonBlockingTraceGenL2Config extends Config(
@@ -31,6 +34,7 @@ class NonBlockingTraceGenL2Config extends Config(
new chipyard.config.WithTracegenSystem ++
new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class NonBlockingTraceGenL2RingConfig extends Config(
@@ -40,4 +44,5 @@ class NonBlockingTraceGenL2RingConfig extends Config(
new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new testchipip.WithRingSystemBus ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

8
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -29,7 +29,6 @@ class TutorialStarterConfig extends Config(
// Config fragments below this line affect hardware generation
// of the Top
new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core
new chipyard.config.WithNoGPIO ++ // Disable GPIOs.
new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM
new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op
new chipyard.config.WithUART ++ // Add a UART
@@ -51,6 +50,7 @@ class TutorialStarterConfig extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
// BaseConfig configures "bare" rocketchip system
new freechips.rocketchip.system.BaseConfig
)
@@ -65,7 +65,6 @@ class TutorialMMIOConfig extends Config(
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithRenumberHarts ++
new chipyard.config.WithUART ++
@@ -81,6 +80,7 @@ class TutorialMMIOConfig extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig
)
@@ -93,7 +93,6 @@ class TutorialSha3Config extends Config(
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithRenumberHarts ++
new chipyard.config.WithUART ++
@@ -107,6 +106,7 @@ class TutorialSha3Config extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig
)
@@ -119,7 +119,6 @@ class TutorialSha3BlackBoxConfig extends Config(
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithRenumberHarts ++
new chipyard.config.WithUART ++
@@ -134,5 +133,6 @@ class TutorialSha3BlackBoxConfig extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig
)

25
generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala Normal file
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@@ -0,0 +1,25 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage
import freechips.rocketchip.stage.ConfigsAnnotation
import firrtl.options.{HasShellOptions, ShellOption}
/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */
private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
override val options = Seq(
new ShellOption[String](
longOption = "legacy-configs",
toAnnotationSeq = a => {
val split = a.split('.')
val packageName = split.init.mkString(".")
val configs = split.last.split("_")
Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } ))
},
helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).",
shortOption = Some("LC")
)
)
}

15
generators/chipyard/src/main/scala/stage/ChipyardCli.scala Normal file
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@@ -0,0 +1,15 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage
import firrtl.options.Shell
trait ChipyardCli { this: Shell =>
parser.note("Chipyard Generator Options")
Seq(
UnderscoreDelimitedConfigsAnnotation
)
.foreach(_.addOptions(parser))
}

36
generators/chipyard/src/main/scala/stage/ChipyardStage.scala Normal file
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@@ -0,0 +1,36 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage
import chisel3.stage.{ChiselCli, ChiselStage}
import firrtl.options.PhaseManager.PhaseDependency
import firrtl.options.{Phase, PreservesAll, Shell}
import firrtl.stage.FirrtlCli
import freechips.rocketchip.stage.RocketChipCli
import freechips.rocketchip.system.RocketChipStage
import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
import firrtl.options.phases.DeletedWrapper
class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
override val targets: Seq[PhaseDependency] = Seq(
Dependency[freechips.rocketchip.stage.phases.Checks],
Dependency[freechips.rocketchip.stage.phases.TransformAnnotations],
Dependency[freechips.rocketchip.stage.phases.PreElaboration],
Dependency[chisel3.stage.phases.Checks],
Dependency[chisel3.stage.phases.Elaborate],
Dependency[freechips.rocketchip.stage.phases.GenerateROMs],
Dependency[chisel3.stage.phases.AddImplicitOutputFile],
Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
Dependency[chisel3.stage.phases.MaybeAspectPhase],
Dependency[chisel3.stage.phases.Emitter],
Dependency[chisel3.stage.phases.Convert],
Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
Dependency[freechips.rocketchip.stage.phases.AddDefaultTests],
Dependency[chipyard.stage.phases.AddDefaultTests],
Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
)
}

67
generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala Normal file
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@@ -0,0 +1,67 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage.phases
import scala.util.Try
import scala.collection.mutable
import chipsalliance.rocketchip.config.Parameters
import chisel3.stage.phases.Elaborate
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}
import firrtl.options.{Phase, PreservesAll, Dependency}
import firrtl.options.Viewer.view
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
import freechips.rocketchip.util.HasRocketChipStageUtils
import freechips.rocketchip.tile.XLen
import chipyard.TestSuiteHelper
class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
// Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
// because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
override val prerequisites = Seq(
Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])
override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])
private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
val annotations = mutable.ArrayBuffer[Annotation]()
val suiteHelper = new TestSuiteHelper
// Use Xlen as a proxy for detecting if we are a processor-like target
// The underlying test suites expect this field to be defined
if (p.lift(XLen).nonEmpty) {
suiteHelper.addRocketTestSuites
suiteHelper.addBoomTestSuites
suiteHelper.addArianeTestSuites
}
// if hwacha parameter exists then generate its tests
// TODO: find a more elegant way to do this. either through
// trying to disambiguate BuildRoCC, having a AccelParamsKey,
// or having the Accelerator/Tile add its own tests
import hwacha.HwachaTestSuites._
if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
suiteHelper.addSuites(rv64uv.map(_("p")))
suiteHelper.addSuites(rv64uv.map(_("vp")))
suiteHelper.addSuite(rv64sv("p"))
suiteHelper.addSuite(hwachaBmarks)
annotations += CustomMakefragSnippet(
"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
}
RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
}
override def transform(annotations: AnnotationSeq): AnnotationSeq = {
val (testSuiteAnnos, oAnnos) = annotations.partition {
case RocketTestSuiteAnnotation(_) => true
case o => false
}
implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance
addTestSuiteAnnotations ++ oAnnos
}
}

49
generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala Normal file
View File

@@ -0,0 +1,49 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage.phases
import scala.collection.mutable
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}
import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency}
import firrtl.options.Viewer.view
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
import freechips.rocketchip.system.TestGeneration
import freechips.rocketchip.util.HasRocketChipStageUtils
trait MakefragSnippet { self: Annotation =>
def toMakefrag: String
}
case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
// Our annotations tend not to be serializable, but are not marked as such.
override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
Dependency[chipyard.stage.phases.AddDefaultTests])
override def transform(annotations: AnnotationSeq): AnnotationSeq = {
val targetDir = view[StageOptions](annotations).targetDir
val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d"
val makefragBuilder = new mutable.StringBuilder()
val outputAnnotations = annotations.flatMap {
case RocketTestSuiteAnnotation(tests) =>
// Unfortunately the gen method of TestGeneration is rocketchip package
// private, so we either have to copy code in or use the stateful form
TestGeneration.addSuites(tests)
None
case a: MakefragSnippet =>
makefragBuilder :+ ("\n" + a.toMakefrag)
None
case a => Some(a)
}
writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)
outputAnnotations
}
}

9
generators/chipyard/src/main/scala/unittest/TestHarness.scala Normal file
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@@ -0,0 +1,9 @@
package chipyard.unittest
import chisel3._
import freechips.rocketchip.config.Parameters
class TestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle { val success = Output(Bool()) })
io.success := Module(new UnitTestSuite).io.finished
}

8
generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala Normal file
View File

@@ -0,0 +1,8 @@
package chipyard.unittest
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}
class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
}

46
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -8,12 +8,12 @@ import chisel3.experimental.annotate
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem}
import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
import icenet.CanHavePeripheryIceNICModuleImp
import junctions.{NastiKey, NastiParameters}
@@ -27,7 +27,8 @@ import ariane.ArianeTile
import boom.common.{BoomTile}
import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
import chipyard.HasChipyardTilesModuleImp
import chipyard.{HasChipyardTilesModuleImp}
import testchipip.{CanHaveTraceIOModuleImp}
object MainMemoryConsts {
val regionNamePrefix = "MainMemory"
@@ -56,30 +57,36 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
class WithFASEDBridge extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => {
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
implicit val p = system.p
(system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) =>
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
axi4Bundle.ar.bits.addr.getWidth,
axi4Bundle.ar.bits.id.getWidth)
FASEDBridge(system.clock, axi4Bundle, system.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
})
(system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
axi4.ar.bits.addr.getWidth,
axi4.ar.bits.id.getWidth)
FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
})
Nil
}
})
class WithTracerVBridge extends OverrideIOBinder({
class WithTracerVBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp) =>
system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
})
class WithDromajoBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp) => {
system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
}
})
class WithTraceGenBridge extends OverrideIOBinder({
(system: HasTraceGenTilesModuleImp) =>
GroundTestBridge(system.clock, system.success)(system.p); Nil
@@ -116,9 +123,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({
class WithTiedOffSystemDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
Debug.tieoffDebug(system.debug, system.psd)
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
// tieoffDebug doesn't actually tie everything off :/
system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
system.debug.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
d.dmactiveAck := DontCare
}
Nil
}
})

20
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -29,19 +29,31 @@ object NodeIdx {
}
class FireSim(implicit val p: Parameters) extends RawModule {
freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
val clockBridge = Module(new RationalClockBridge)
val clock = clockBridge.io.clocks.head
val reset = WireInit(false.B)
withClockAndReset(clock, reset) {
// Instantiate multiple instances of the DUT to implement supernode
val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
val targets = Seq.fill(p(NumNodes)) {
// It's not a RC bump without some hacks...
// Copy the AsyncClockGroupsKey to generate a fresh node on each
// instantiation of the dut, otherwise the initial instance will be
// reused across each node
import freechips.rocketchip.subsystem.AsyncClockGroupsKey
val lazyModule = p(BuildSystem)(p.alterPartial({
case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
}))
(lazyModule, Module(lazyModule.module))
}
val peekPokeBridge = PeekPokeBridge(clock, reset)
// A Seq of partial functions that will instantiate the right bridge only
// if that Mixin trait is present in the target's class instance
// if that Mixin trait is present in the target's LazyModule class instance
//
// Apply each partial function to each DUT instance
for ((target) <- targets) {
p(IOBinders).values.map(_(target))
for ((lazyModule, module) <- targets) {
p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
NodeIdx.increment()
}
}

15
generators/firechip/src/main/scala/FireSimMulticlockPOC.scala
View File

@@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config
class HalfRateUncore extends WithSingleRationalTileDomain(2,1)
class WithFiresimMulticlockTop extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module)
case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system")
})
// Complete Config
@@ -79,25 +79,30 @@ class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop
override lazy val module = new FiresimMulticlockTopModule(this)
}
class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp
// Harness Definition
class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
val refClock = clockBridge.io.clocks.head
val reset = WireInit(false.B)
withClockAndReset(refClock, reset) {
// Instantiate multiple instances of the DUT to implement supernode
val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
val targets = Seq.fill(p(NumNodes)) {
val lazyModule = p(BuildSystem)(p)
(lazyModule, Module(lazyModule.module))
}
val peekPokeBridge = PeekPokeBridge(refClock, reset)
// A Seq of partial functions that will instantiate the right bridge only
// if that Mixin trait is present in the target's class instance
//
// Apply each partial function to each DUT instance
for ((target) <- targets) {
p(IOBinders).values.map(_(target))
for ((lazyModule, module) <- targets) {
p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
}
targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks })
}
}

79
generators/firechip/src/main/scala/Generator.scala
View File

@@ -1,79 +0,0 @@
//See LICENSE for license details.
package firesim.firesim
import java.io.{File, FileWriter}
import chisel3.RawModule
import chisel3.internal.firrtl.{Circuit, Port}
import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
import freechips.rocketchip.devices.debug.DebugIO
import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
import freechips.rocketchip.system.DefaultTestSuites._
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.subsystem.RocketTilesKey
import freechips.rocketchip.tile.XLen
import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
import scala.util.Try
import chipyard.TestSuiteHelper
trait HasTestSuites {
def addTestSuites(targetName: String, params: Parameters) {
TestSuiteHelper.addRocketTestSuites(params)
TestSuiteHelper.addBoomTestSuites(params)
TestSuiteHelper.addArianeTestSuites(params)
TestGeneration.addSuite(FastBlockdevTests)
TestGeneration.addSuite(SlowBlockdevTests)
if (!targetName.contains("NoNIC"))
TestGeneration.addSuite(NICLoopbackTests)
import hwacha.HwachaTestSuites._
if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
TestGeneration.addSuites(rv64uv.map(_("p")))
TestGeneration.addSuites(rv64uv.map(_("vp")))
TestGeneration.addSuite(rv64sv("p"))
TestGeneration.addSuite(hwachaBmarks)
}
}
}
// Mixed into an App or into a TestSuite
trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites {
/** Output software test Makefrags, which provide targets for integration testing. */
def generateTestSuiteMakefrags {
addTestSuites(names.topModuleClass, targetParams)
writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites
}
// Output miscellaneous files produced as a side-effect of elaboration
def generateArtefacts {
ElaborationArtefacts.files.foreach { case (extension, contents) =>
writeOutputFile(s"${longName}.${extension}", contents ())
}
}
}
object FireSimGenerator extends App with IsFireSimGeneratorLike {
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
lazy val generatorArgs = GeneratorArgs(args)
lazy val genDir = new File(names.targetDir)
// The only reason this is not generateFirrtl; generateAnno is that we need to use a different
// JsonProtocol to properly write out the annotations. Fix once the generated are unified
elaborate
generateTestSuiteMakefrags
generateArtefacts
}
// For now, provide a separate generator app when not specifically building for FireSim
object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}

19
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -41,17 +41,15 @@ class WithBootROM extends Config((site, here, up) => {
})
class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => {
case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
})
class WithPerfCounters extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
core = tile.core.copy(nPerfCounters = 29)
))
})
// Disables clock-gating; doesn't play nice with our FAME-1 pass
class WithoutClockGating extends Config((site, here, up) => {
case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
@@ -63,7 +61,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
})
// FASED Config Aliases. This to enable config generation via "_" concatenation
// which requires that all config classes be defined in the same package
class DDR3FRFCFS extends FRFCFS16GBQuadRank
@@ -71,14 +68,9 @@ class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
// Enables tracing on all cores
class WithTraceIO extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
})
// Adds a small/large NVDLA to the system
class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large")
class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")
// Tweaks that are generally applied to all firesim configs
@@ -92,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
// Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
new WithoutTLMonitors ++
// Optional: Adds IO to attach tracerV bridges
new WithTraceIO ++
new chipyard.config.WithTraceIO ++
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
@@ -143,7 +135,6 @@ class FireSimLargeBoomConfig extends Config(
new WithFireSimConfigTweaks ++
new chipyard.LargeBoomConfig)
//********************************************************************
// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
//********************************************************************

112
generators/firechip/src/test/scala/ScalaTestSuite.scala
View File

@@ -6,44 +6,34 @@ import java.io.File
import scala.concurrent.{Future, Await, ExecutionContext}
import scala.sys.process.{stringSeqToProcess, ProcessLogger}
import scala.io.Source
import org.scalatest.Suites
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite}
import freechips.rocketchip.system.TestGeneration._
import freechips.rocketchip.system.DefaultTestSuites._
import firesim.util.GeneratorArgs
abstract class FireSimTestSuite(
topModuleClass: String,
targetConfigs: String,
platformConfigs: String,
N: Int = 8
) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
) extends firesim.TestSuiteCommon {
import scala.concurrent.duration._
import ExecutionContext.Implicits.global
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
val topModuleProject = "firesim.firesim"
lazy val generatorArgs = GeneratorArgs(
midasFlowKind = "midas",
targetDir = "generated-src",
topModuleProject = "firesim.firesim",
topModuleClass = topModuleClass,
targetConfigProject = "firesim.firesim",
targetConfigs = targetConfigs ++ "_WithScalaTestFeatures",
platformConfigProject = "firesim.firesim",
platformConfigs = platformConfigs)
// From HasFireSimGeneratorUtilities
// For the firesim utilities to use the same directory as the test suite
override lazy val testDir = genDir
val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs
// From TestSuiteCommon
val targetTuple = generatorArgs.tupleName
val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs"
val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}",
s"TARGET_CONFIG=${targetConfigs}",
s"PLATFORM_CONFIG=${platformConfigs}")
override lazy val genDir = new File(firesimDir, s"generated-src/${chipyardLongName}")
def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
@@ -61,12 +51,6 @@ abstract class FireSimTestSuite(
}
}
//def runReplay(backend: String, replayBackend: String, name: String) = {
// val dir = (new File(outDir, backend)).getAbsolutePath
// (Seq("make", s"replay-$replayBackend",
// s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).!
//}
def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) {
// compile emulators
behavior of s"${suite.makeTargetName} running on $backend"
@@ -75,7 +59,7 @@ abstract class FireSimTestSuite(
case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
case _ => ""
}
val results = suite.names.toSeq sliding (N, N) map { t =>
val results = suite.names.toSeq sliding (N, N) map { t =>
val subresults = t map (name =>
Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
Await result (Future sequence subresults, Duration.Inf)
@@ -83,20 +67,6 @@ abstract class FireSimTestSuite(
results.flatten foreach { case (name, exitcode) =>
it should s"pass $name" in { assert(exitcode == 0) }
}
//replayBackends foreach { replayBackend =>
// if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) {
// assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs
// suite.names foreach { name =>
// it should s"replay $name in $replayBackend" in {
// assert(runReplay(backend, replayBackend, s"$name$postfix") == 0)
// }
// }
// } else {
// suite.names foreach { name =>
// ignore should s"replay $name in $backend"
// }
// }
//}
} else {
ignore should s"pass $backend"
}
@@ -127,62 +97,24 @@ abstract class FireSimTestSuite(
}
clean
mkdirs
elaborate
generateTestSuiteMakefrags
runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
//diffTracelog("rv64ui-p-simple.out")
runSuite("verilator")(benchmarks)
runSuite("verilator")(FastBlockdevTests)
}
class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config")
class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
runSuite("verilator")(NICLoopbackTests)
}
// Disabled until RAM optimizations re-enabled in multiclock
//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams")
//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams")
class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config")
// Multiclock tests
class RocketMulticlockF1Tests extends FireSimTestSuite(
"FireSimMulticlockPOC",
"FireSimQuadRocketMulticlockConfig",
"WithSynthAsserts_BaseF1Config")
// Jerry broke these -- damn it Jerry.
//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
//
// lazy val generatorArgs = GeneratorArgs(
// midasFlowKind = "midas",
// targetDir = "generated-src",
// topModuleProject = "firesim.firesim",
// topModuleClass = "FireSimTraceGen",
// targetConfigProject = "firesim.firesim",
// targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
// platformConfigProject = "firesim.firesim",
// platformConfigs = platformConfig)
//
// // From HasFireSimGeneratorUtilities
// // For the firesim utilities to use the same directory as the test suite
// override lazy val testDir = genDir
//
// // From TestSuiteCommon
// val targetTuple = generatorArgs.tupleName
// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
// s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
//
// it should "pass" in {
// assert(make("fsim-tracegen") == 0)
// }
//}
//
//class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
//
//class FireSimL2TraceGenTest extends FireSimTraceGenTest(
// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")
class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
class CITests extends Suites(
new RocketF1Tests,
new BoomF1Tests,
new RocketNICF1Tests,
new RocketMulticlockF1Tests)

2
generators/hwacha

Submodule generators/hwacha updated: ef5e5196b6...2706502daf

2
generators/icenet

Submodule generators/icenet updated: b1f957e6eb...705ca50690

1
generators/nvdla Submodule

Submodule generators/nvdla added at b2b78c9f89

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 4f0cdea85c...1872f5d501

2
generators/sifive-blocks

Submodule generators/sifive-blocks updated: 1bc0ef18d6...c1dee8234c

2
generators/sifive-cache

Submodule generators/sifive-cache updated: d3d95ece5a...4ebefa3e30

2
generators/testchipip

Submodule generators/testchipip updated: d06d7c7dc2...b02bd8eaca

2
generators/tracegen/src/main/scala/System.scala
View File

@@ -41,7 +41,6 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp {
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with HasTraceGenTiles
with HasHierarchicalBusTopology
with CanHaveMasterAXI4MemPort {
override lazy val module = new TraceGenSystemModuleImp(this)
}
@@ -49,4 +48,3 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
class TraceGenSystemModuleImp(outer: TraceGenSystem)
extends BaseSubsystemModuleImp(outer)
with HasTraceGenTilesModuleImp
with CanHaveMasterAXI4MemPortModuleImp

13
generators/tracegen/src/main/scala/Tile.scala
View File

@@ -86,7 +86,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
io.lsu.dis_uops(0).valid := io.tracegen.req.fire()
io.lsu.dis_uops(0).bits := tracegen_uop
when (io.tracegen.req.fire()) {
rob_tail := WrapInc(rob_tail, rob_sz)
rob_bsy(rob_tail) := true.B
@@ -165,8 +165,15 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
io.lsu.rob_pnr_idx := rob_tail
io.lsu.commit_load_at_rob_head := false.B
io.lsu.brinfo := DontCare
io.lsu.brinfo.valid := false.B
io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.exu.BrUpdateMasks)
io.lsu.brupdate.b2.uop := DontCare
io.lsu.brupdate.b2.mispredict := false.B
io.lsu.brupdate.b2.taken := false.B
io.lsu.brupdate.b2.cfi_type := 0.U
io.lsu.brupdate.b2.pc_sel := 0.U
io.lsu.brupdate.b2.jalr_target := 0.U
io.lsu.brupdate.b2.target_offset := 0.S(2.W)
io.lsu.rob_head_idx := rob_head

10
generators/utilities/src/main/resources/csrc/emulator.cc
View File

@@ -38,8 +38,8 @@ extern remote_bitbang_t * jtag;
extern int dramsim;
static uint64_t trace_count = 0;
bool verbose;
bool done_reset;
bool verbose = false;
bool done_reset = false;
void handle_sigterm(int sig)
{
@@ -282,8 +282,12 @@ done_processing:
signal(SIGTERM, handle_sigterm);
bool dump;
// start reset off low so a rising edge triggers async reset
tile->reset = 0;
tile->clock = 0;
tile->eval();
// reset for several cycles to handle pipelined reset
for (int i = 0; i < 10; i++) {
for (int i = 0; i < 100; i++) {
tile->reset = 1;
tile->clock = 0;
tile->eval();