Merge remote-tracking branch 'origin/dev' into HEAD

2020-05-23 22:49:51 +00:00
parent 0cc643bfdb c2c9bc83de
commit f56e367d59
101 changed files with 8537 additions and 708 deletions
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -6,13 +6,13 @@ version: 2.1
 parameters:
    tools-cache-version:
        type: string
-        default: "v4"
+        default: "v5"

 # default execution env.s
 executors:
    main-env:
        docker:
-            - image: ucbbar/chipyard-image:1.0.0
+            - image: ucbbar/chipyard-image:1.0.1
        environment:
            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit

@@ -247,23 +247,36 @@ jobs:
        steps:
            - prepare-rtl:
                project-key: "tracegen-boom"
-    prepare-firesim:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "firesim"
-                build-script: "do-firesim-build.sh"
-    prepare-fireboom:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "fireboom"
-                build-script: "do-firesim-build.sh"
    prepare-chipyard-ariane:
        executor: main-env
        steps:
            - prepare-rtl:
                project-key: "chipyard-ariane"
+    prepare-icenet:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "icenet"
+    prepare-testchipip:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "testchipip"
+    prepare-chipyard-nvdla:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-nvdla"
+    prepare-chipyard-spiflashwrite:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-spiflashwrite"
+    prepare-chipyard-spiflashread:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-spiflashread"
    chipyard-rocket-run-tests:
        executor: main-env
        steps:
@@ -279,6 +292,7 @@ jobs:
        steps:
            - run-tests:
                project-key: "chipyard-hetero"
+                timeout: "15m"
    chipyard-boom-run-tests:
        executor: main-env
        steps:
@@ -301,6 +315,16 @@ jobs:
            - run-tests:
                tools-version: "esp-tools"
                project-key: "chipyard-gemmini"
+    chipyard-spiflashwrite-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "chipyard-spiflashwrite"
+    chipyard-spiflashread-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "chipyard-spiflashread"
    tracegen-run-tests:
        executor: main-env
        steps:
@@ -317,15 +341,24 @@ jobs:
            - run-tests:
                extra-cache-restore: "extra-tests"
                project-key: "firesim"
-                run-script: "run-firesim-tests.sh"
+                run-script: "run-firesim-scala-tests.sh"
+                timeout: "20m"
    fireboom-run-tests:
        executor: main-env
        steps:
            - run-tests:
                extra-cache-restore: "extra-tests"
                project-key: "fireboom"
-                run-script: "run-firesim-tests.sh"
-                timeout: "30m"
+                run-script: "run-firesim-scala-tests.sh"
+                timeout: "45m"
+    firesim-multiclock-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                extra-cache-restore: "extra-tests"
+                project-key: "firesim-multiclock"
+                run-script: "run-firesim-scala-tests.sh"
+                timeout: "20m"
    midasexamples-run-tests:
        executor: main-env
        steps:
@@ -333,11 +366,30 @@ jobs:
            - run:
                name: Run midasexamples tests
                command: .circleci/run-midasexamples-tests.sh
+                no_output_timeout: 20m
    chipyard-ariane-run-tests:
        executor: main-env
        steps:
            - run-tests:
                project-key: "chipyard-ariane"
+                timeout: "30m"
+    chipyard-nvdla-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "chipyard-nvdla"
+    icenet-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "icenet"
+                timeout: "30m"
+    testchipip-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "testchipip"
+                timeout: "30m"

 # Order and dependencies of jobs to run
 workflows:
@@ -427,21 +479,36 @@ workflows:
                    - install-riscv-toolchain
                    - install-verilator

-            - prepare-firesim:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-fireboom:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
            - prepare-chipyard-ariane:
                requires:
                    - install-riscv-toolchain
                    - install-verilator

+            - prepare-icenet:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
+            - prepare-testchipip:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
+            - prepare-chipyard-nvdla:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
+            - prepare-chipyard-spiflashwrite:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
+            - prepare-chipyard-spiflashread:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
            # Run the respective tests

            # Run midasexamples test
@@ -486,17 +553,42 @@ workflows:
                requires:
                    - prepare-tracegen-boom

+            - chipyard-spiflashwrite-run-tests:
+                requires:
+                    - prepare-chipyard-spiflashwrite
+
+            - chipyard-spiflashread-run-tests:
+                requires:
+                    - prepare-chipyard-spiflashread
+
            # Run the firesim tests
            - firesim-run-tests:
                requires:
-                    - prepare-firesim
+                    - install-riscv-toolchain
+                    - install-verilator
+                    - build-extra-tests
+            - firesim-multiclock-run-tests:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
                    - build-extra-tests
-
            - fireboom-run-tests:
                requires:
-                    - prepare-fireboom
+                    - install-riscv-toolchain
+                    - install-verilator
                    - build-extra-tests

            - chipyard-ariane-run-tests:
                requires:
                    - prepare-chipyard-ariane
+
+            - chipyard-nvdla-run-tests:
+                requires:
+                    - prepare-chipyard-nvdla
+            - icenet-run-tests:
+                requires:
+                    - prepare-icenet
+
+            - testchipip-run-tests:
+                requires:
+                    - prepare-testchipip
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -21,7 +21,7 @@ clean () {
 NPROC=8

 # verilator version
-VERILATOR_VERSION=v4.028
+VERILATOR_VERSION=v4.034

 # remote variables
 REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB
@@ -30,7 +30,8 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install
 REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
 REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
 REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
-REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
+# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI
+REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
 REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install

 # local variables (aka within the docker container)
@@ -47,13 +48,17 @@ mapping["chipyard-rocket"]="SUB_PROJECT=chipyard"
 mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig"
 mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig"
 mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig"
-mapping["rocketchip"]="SUB_PROJECT=rocketchip"
 mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig"
 mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig"
+mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig"
+mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig"
+mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig"
 mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
 mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
-mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config"
-mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config"
-mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig"
-mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config"
+mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig"
+mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
+mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
+mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
+mapping["icenet"]="SUB_PROJECT=icenet"
+mapping["testchipip"]="SUB_PROJECT=testchipip"
--- a/.circleci/images/Dockerfile
+++ b/.circleci/images/Dockerfile
@@ -13,6 +13,8 @@ RUN apt-get update \
               git \
               gnupg \
               gzip \
+               libfl2 \
+               libfl-dev \
               locales \
               mercurial \
               netcat \
@@ -24,7 +26,12 @@ RUN apt-get update \
               unzip \
               wget \
               xvfb \
-               zip
+               xxd \
+               zip \
+               ccache \
+               libgoogle-perftools-dev \
+               numactl \
+               zlib1g

 # Set timezone to UTC by default
 RUN ln -sf /usr/share/zoneinfo/Etc/UTC /etc/localtime
@@ -127,34 +134,46 @@ RUN apt-get install -y --no-install-recommends openjfx
 RUN apt-get install -y build-essential

 # Add RISCV toolchain necessary dependencies
+RUN apt-get update
 RUN apt-get install -y \
            autoconf \
            automake \
            autotools-dev \
            babeltrace \
            bc \
-            bison \
            curl \
            device-tree-compiler \
            expat \
            flex \
            gawk \
            gperf \
+            g++ \
            libexpat-dev \
            libgmp-dev \
            libmpc-dev \
            libmpfr-dev \
            libtool \
            libusb-1.0-0-dev \
+            make \
            patchutils \
            pkg-config \
            python \
-            python-pexpect \
+            python-pexpect-doc \
            python3 \
            texinfo \
            zlib1g-dev \
            rsync

+# Use specific bison version to bypass Verilator 4.034 issues
+# TODO: When Verilator is bumped, use apt to get newest bison
+RUN wget https://ftp.gnu.org/gnu/bison/bison-3.5.4.tar.gz \
+    && tar -xvf bison-3.5.4.tar.gz \
+    && cd bison-3.5.4 \
+    && ./configure && make && make install
+
+# Check bison version is 3.5.4
+RUN bison --version
+
 # Add minimal QEMU dependencies
 RUN apt-get install -y \
            libfdt-dev \
@@ -164,7 +183,8 @@ RUN apt-get install -y \
 # Install verilator
 RUN git clone http://git.veripool.org/git/verilator \
    && cd verilator \
-    && git checkout v4.028 \
+    && git pull \
+    && git checkout v4.034 \
    && autoconf && ./configure && make && make install

 # Update PATH for Java tools
--- a/.circleci/run-firesim-scala-tests.sh
+++ b/.circleci/run-firesim-scala-tests.sh
@@ -22,6 +22,7 @@ cd $LOCAL_CHIPYARD_DIR/sims/firesim
 ./scripts/build-libdwarf.sh
 cd $LOCAL_CHIPYARD_DIR

+make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src

 # set stricthostkeychecking to no (must happen before rsync)
 run "echo \"Ping $SERVER\""
@@ -30,7 +31,9 @@ clean

 # copy over riscv/esp-tools, and chipyard to remote
 run "mkdir -p $REMOTE_CHIPYARD_DIR"
+run "mkdir -p $REMOTE_RISCV_DIR"
 copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
+copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR

 run "cp -r ~/.ivy2 $REMOTE_WORK_DIR"
 run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
@@ -38,31 +41,11 @@ run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
 TOOLS_DIR=$REMOTE_RISCV_DIR
 LD_LIB_DIR=$REMOTE_RISCV_DIR/lib

-if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then
-    TOOLS_DIR=$REMOTE_ESP_DIR
-    LD_LIB_DIR=$REMOTE_ESP_DIR/lib
-    run "mkdir -p $REMOTE_ESP_DIR"
-    copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR
-else
-    run "mkdir -p $REMOTE_RISCV_DIR"
-    copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
-fi

-# Build MIDAS-level verilator sim
-FIRESIM_VARS="${mapping[$1]}"
-run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean"
+# Run Firesim Scala Tests
 run "export RISCV=\"$TOOLS_DIR\"; \
     export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
+     export FIRESIM_ENV_SOURCED=1; \
     export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
     export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
-     export FIRESIM_ENV_SOURCED=1; \
-     make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator"
-run "rm -rf $REMOTE_CHIPYARD_DIR/project"
-
-# copy back the final build
-mkdir -p $LOCAL_CHIPYARD_DIR
-copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR
-
-# Fix dramsim2_ini symlink
-export $FIRESIM_VARS
-ln -sf $LOCAL_FIRESIM_DIR/midas/src/main/resources/dramsim2_ini $LOCAL_FIRESIM_DIR/generated-src/f1/${DESIGN}-${TARGET_CONFIG}-${PLATFORM_CONFIG}/dramsim2_ini
+     make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}"
--- a/.circleci/run-firesim-tests.sh
+++ b/.circleci/run-firesim-tests.sh
@@ -1,29 +0,0 @@
-#!/bin/bash
-
-# turn echo on and error on earliest command
-set -ex
-
-# get remote exec variables
-SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
-source $SCRIPT_DIR/defaults.sh
-
-export FIRESIM_ENV_SOURCED=1
-
-SIMULATION_ARGS="${mapping[$1]}"
-
-cd $LOCAL_CHIPYARD_DIR/sims/firesim
-./scripts/build-libelf.sh
-./scripts/build-libdwarf.sh
-cd $LOCAL_CHIPYARD_DIR
-
-
-run_test_suite () {
-    export RISCV=$LOCAL_RISCV_DIR
-    export LD_LIBRARY_PATH=$LOCAL_RISCV_DIR/lib
-    make -C $LOCAL_FIRESIM_DIR $SIMULATION_ARGS run-${1}-tests-fast
-}
-
-
-run_test_suite bmark
-run_test_suite nic
-run_test_suite blockdev
--- a/.circleci/run-midasexamples-tests.sh
+++ b/.circleci/run-midasexamples-tests.sh
@@ -12,6 +12,10 @@ trap clean EXIT

 cd $LOCAL_CHIPYARD_DIR
 ./scripts/init-submodules-no-riscv-tools.sh
+
+# build libdromajo_cosim
+make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src
+
 cd sims/firesim/sim/midas

 # set stricthostkeychecking to no (must happen before rsync)
--- a/.circleci/run-tests.sh
+++ b/.circleci/run-tests.sh
@@ -62,6 +62,15 @@ case $1 in
        (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
        $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv
        ;;
+    chipyard-spiflashread)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary
+        ;;
+    chipyard-spiflashwrite)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary
+        [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img  | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false
+        ;;
    tracegen)
        run_tracegen ${mapping[$1]}
        ;;
@@ -71,6 +80,16 @@ case $1 in
    chipyard-ariane)
        make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
        ;;
+    chipyard-nvdla)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary
+        ;;
+    icenet)
+        make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]}
+        ;;
+    testchipip)
+        make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]}
+        ;;
    *)
        echo "No set of tests for $1. Did you spell it right?"
        exit 1
--- a/.github/ISSUE_TEMPLATE/bug-report.md
+++ b/.github/ISSUE_TEMPLATE/bug-report.md
@@ -8,16 +8,14 @@ labels: bug
 <!-- choose one -->
 **Impact**: rtl | software | unknown | other

+**Tell us about your environment:**
+*Chipyard Version:* <!-- 1.2.0, Hash: 2c0928 -->
+*OS:* <!-- `Linux knight 4.4.0-92-generic #115-Ubuntu SMP Thu Aug 10 09:04:33 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux` -->
+*Other:* <!-- `prior steps taken/documentation followed/...` -->
+
 **What is the current behavior?**

 **What is the expected behavior?**

-**Please tell us about your environment:**
-<!--    (examples)
-    - version: `chipyard git commit hash`
-    - os: `Linux knight 4.4.0-92-generic #115-Ubuntu SMP Thu Aug 10 09:04:33 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux`
-    - other: `prior steps taken/documentation followed/...`
-->
-
 **Other information**
 <!-- include detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, ... -->
--- a/.github/ISSUE_TEMPLATE/question.md
+++ b/.github/ISSUE_TEMPLATE/question.md
@@ -5,6 +5,11 @@ labels: question

 ---

+<!--
+    this type of issue is more for "how-tos", understanding chipyard, etc.
+    if you find an error or issue with chipyard, please use the "Bug Report Issue".
+-->
+
 <!-- have you looked at the Chipyard documentation? -->
 <!-- have you looked at the subproject documentation/githubs? -->
 <!-- for example: -->
--- a/.gitmodules
+++ b/.gitmodules
@@ -119,3 +119,12 @@
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git
+[submodule "generators/nvdla"]
+	path = generators/nvdla
+	url = https://github.com/ucb-bar/nvdla-wrapper.git
+[submodule "software/nvdla-workload"]
+	path = software/nvdla-workload
+	url = https://github.com/ucb-bar/nvdla-workload.git
+[submodule "tools/dromajo/dromajo-src"]
+	path = tools/dromajo/dromajo-src
+	url = https://github.com/riscv-boom/dromajo.git
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati

 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].

@@ -65,3 +65,4 @@ These publications cover many of the internal components used in Chipyard. Howev
 [firemarshal]: https://github.com/firesim/FireMarshal/
 [ariane]: https://github.com/pulp-platform/ariane/
 [gemmini]: https://github.com/ucb-bar/gemmini
+[nvdla]: http://nvdla.org/
--- a/build.sbt
+++ b/build.sbt
@@ -2,7 +2,7 @@ import Tests._

 // This gives us a nicer handle  to the root project instead of using the
 // implicit one
-lazy val chipyardRoot = RootProject(file("."))
+lazy val chipyardRoot = Project("chipyardRoot", file("."))

 lazy val commonSettings = Seq(
  organization := "edu.berkeley.cs",
@@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
  .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
    sha3, // On separate line to allow for cleaner tutorial-setup patches
    dsptools, `rocket-dsptools`,
-    gemmini, icenet, tracegen, ariane)
+    gemmini, icenet, tracegen, ariane, nvdla)
  .settings(commonSettings)

 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
@@ -150,7 +150,7 @@ lazy val hwacha = (project in file("generators/hwacha"))
  .dependsOn(rocketchip)
  .settings(commonSettings)

-lazy val boom = (project in file("generators/boom"))
+lazy val boom = conditionalDependsOn(project in file("generators/boom"))
  .dependsOn(rocketchip)
  .settings(commonSettings)

@@ -166,9 +166,14 @@ lazy val gemmini = (project in file("generators/gemmini"))
  .dependsOn(rocketchip, chisel_testers, testchipip)
  .settings(commonSettings)

+lazy val nvdla = (project in file("generators/nvdla"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
 lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
  .dependsOn(chisel_testers, chipyard)
  .settings(commonSettings)
+  .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0"))

 lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
  .settings(commonSettings)
--- a/common.mk
+++ b/common.mk
@@ -14,10 +14,13 @@ SHELL=/bin/bash
 #########################################################################################
 include $(base_dir)/generators/ariane/ariane.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
+include $(base_dir)/generators/nvdla/nvdla.mk
+include $(base_dir)/tools/dromajo/dromajo.mk

 #########################################################################################
-# variables to get all *.scala files
+# Prerequisite lists
 #########################################################################################
+# Returns a list of files in directory $1 with file extension $2.
 lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null)

 SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell)
@@ -35,17 +38,24 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class
 # jar creation variables and rules
 #########################################################################################
 FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
+FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar

-$(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala)
+$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
 	$(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala
 	mkdir -p $(@D)
 	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@
 	touch $@

+$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
+	cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly"
+	mkdir -p $(@D)
+	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
+	touch $@
+
 #########################################################################################
 # create list of simulation file inputs
 #########################################################################################
-$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR)
+$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR)
 	cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"

 #########################################################################################
@@ -58,7 +68,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp
 # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
 generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
 	mkdir -p $(build_dir)
-	cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
+	cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \
+		--target-dir $(build_dir) \
+		--name $(long_name) \
+		--top-module $(MODEL_PACKAGE).$(MODEL) \
+		--legacy-configs $(CONFIG_PACKAGE).$(CONFIG)"

 .PHONY: firrtl
 firrtl: $(FIRRTL_FILE)
@@ -132,6 +146,12 @@ run-binary-debug: $(sim_debug)

 run-fast: run-asm-tests-fast run-bmark-tests-fast

+run-none: $(output_dir)/none.out
+
+run-none-fast: $(output_dir)/none.run
+
+run-none-debug: $(output_dir)/none.vpd
+
 #########################################################################################
 # run assembly/benchmarks rules
 #########################################################################################
@@ -145,6 +165,14 @@ $(output_dir)/%.run: $(output_dir)/% $(sim)
 $(output_dir)/%.out: $(output_dir)/% $(sim)
 	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)

+$(output_dir)/none.run: $(sim)
+	mkdir -p $(output_dir)
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
+
+$(output_dir)/none.out: $(sim)
+	mkdir -p $(output_dir)
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $@) | tee $(output_dir)/none.log)
+
 #########################################################################################
 # include build/project specific makefrags made from the generator
 #########################################################################################
--- a/docs/Advanced-Concepts/Debugging-BOOM.rst
+++ b/docs/Advanced-Concepts/Debugging-BOOM.rst
@@ -0,0 +1,30 @@
+Debugging BOOM
+======================
+
+In addition to the default debugging techniques specified in :ref:`Debugging RTL`,
+single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Dromajo`)
+to verify functionality.
+
+.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators.
+
+.. warning:: Dromajo currently only works in VCS simulation and FireSim.
+
+Setting up Dromajo Co-simulation
+--------------------------------------
+
+Dromajo co-simulation is setup to work when two config fragments are added to a BOOM config.
+First, a ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled.
+Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config fragment must be added to
+connect the Dromajo co-simulator to the traceport.
+Once both config fragments are added Dromajo should be enabled.
+
+To build/run Dromajo with a BOOM design, run your configuration the following make commands:
+
+.. code-block:: shell
+
+    # build the default Dromajo BOOM config without waveform dumps
+    # replace "DromajoBoomConfig" with your particular config
+    make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1
+
+    # run a simulation with Dromajo
+    make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY=<YOUR-BIN> run-binary
--- a/docs/Advanced-Concepts/Debugging-RTL.rst
+++ b/docs/Advanced-Concepts/Debugging-RTL.rst
@@ -88,7 +88,7 @@ directory.

 Firesim Debugging
 ---------------------------
-Chisel printfs, asserts, and waveform generation are also available in FireSim
+Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim
 FPGA-accelerated simulation. See the FireSim
 `documentation <https://docs.fires.im/en/latest/>`__ for more detail.

--- a/docs/Advanced-Concepts/index.rst
+++ b/docs/Advanced-Concepts/index.rst
@@ -11,6 +11,7 @@ They expect you to know about Chisel, Parameters, configs, etc.
   Top-Testharness
   Chip-Communication
   Debugging-RTL
+   Debugging-BOOM
   Resources
   CDEs

--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -79,6 +79,10 @@ Tools
 **Dsptools**
  A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).

+**Dromajo**
+  A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technologies.
+  See :ref:`Dromajo` for more information.
+
 Toolchains
 -------------------------------------------

--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -23,10 +23,10 @@ In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following

 .. Note:: When running on an Amazon Web Services EC2 FPGA-development instance (for FireSim), FireSim includes a machine setup script that will install all of the aforementioned dependencies (and some additional ones).

-Checking out the sources
------------------------
+Setting up the Chipyard Repo
+-------------------------------------------

-After cloning this repo, you will need to initialize all of the submodules.
+Start by fetching Chipyard's sources. Run:

 .. code-block:: shell

@@ -34,6 +34,8 @@ After cloning this repo, you will need to initialize all of the submodules.
    cd chipyard
    ./scripts/init-submodules-no-riscv-tools.sh

+This will initialize and checkout all of the necessary git submodules.
+
 When updating Chipyard to a new version, you will also want to rerun this script to update the submodules.
 Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior.

@@ -46,15 +48,66 @@ The `toolchains` directory contains toolchains that include a cross-compiler too
 Currently there are two toolchains, one for normal RISC-V programs, and another for Hwacha (``esp-tools``).
 For custom installations, Each tool within the toolchains contains individual installation procedures within its README file.
 To get a basic installation (which is the only thing needed for most Chipyard use-cases), just the following steps are necessary.
+This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``.

 .. code-block:: shell

    ./scripts/build-toolchains.sh riscv-tools # for a normal risc-v toolchain

-    # OR
-
-    ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions
+.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above.
+  If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain.

 Once the script is run, a ``env.sh`` file is emitted that sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables.
-You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables.
+You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment:
+
+.. code-block:: shell
+
+    source ./env.sh
+
 These variables need to be set for the ``make`` system to work properly.
+
+What's Next?
+-------------------------------------------
+
+This depends on what you are planning to do with Chipyard.
+
+* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions.
+
+* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions.
+
+* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions.
+
+* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions.
+
+* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`.
+
+* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`.
+
+* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions.
+
+* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions.
+
+Upgrading Chipyard Release Versions
+-------------------------------------------
+
+In order to upgrade between Chipyard versions, we recommend using a fresh clone of the repository (or your fork, with the new release merged into it).
+
+
+Chipyard is a complex framework that depends on a mix of build systems and scripts. Specifically, it relies on git submodules, on sbt build files, and on custom written bash scripts and generated files.
+For this reason, upgrading between Chipyard versions is **not** as trivial as just running ``git submodule update -recursive``. This will result in recursive cloning of large submodules that are not necessarily used within your specific Chipyard environments. Furthermore, it will not resolve the status of stale state generated files which may not be compatible between release versions.
+
+
+If you are an advanced git user, an alternative approach to a fresh repository clone may be to run ``git clean -dfx``, and then run the standard Chipyard setup sequence. This approach is dangerous, and **not-recommended** for users who are not deeply familiar with git, since it "blows up" the repository state and removes all untracked and modified files without warning. Hence, if you were working on custom un-committed changes, you would lose them.
+
+If you would still like to try to perform an in-place manual version upgrade (**not-recommended**), we recommend at least trying to resolve stale state in the following areas:
+
+* Delete stale ``target`` directories generated by sbt.
+
+* Delete jar collateral generated by FIRRTL (``lib/firrtl.jar``)
+
+* Re-generate generated scripts and source files (for example, ``env.sh``)
+
+* Re-generating/deleting target software state (Linux kernel binaries, Linux images) within FireMarshal
+
+
+This is by no means a comprehensive list of potential stale state within Chipyard. Hence, as mentioned earlier, the recommended method for a Chipyard version upgrade is a fresh clone (or a merge, and then a fresh clone).
--- a/docs/Customization/Heterogeneous-SoCs.rst
+++ b/docs/Customization/Heterogeneous-SoCs.rst
@@ -40,13 +40,13 @@ The config fragment to add to your system would look something like the followin
        val boomTile1 = BoomTileParams(...) // params for boom core 1
        val boomTile2 = BoomTileParams(...) // params for boom core 2
        val boomTile3 = BoomTileParams(...) // params for boom core 3
-        boomTile0 ++ boomTile1 ++ boomTile2 ++ boomTile3
+        Seq(boomTile0, boomTile1, boomTile2, boomTile3)
      }

      case RocketTilesKey => {
        val rocketTile0 = RocketTileParams(...) // params for rocket core 0
        val rocketTile1 = RocketTileParams(...) // params for rocket core 1
-        rocketTile0 ++ rocketTile1
+        Seq(rocketTile0, rocketTile1)
      }
    })

@@ -56,7 +56,6 @@ Then you could use this new config fragment like the following.

    class SixCoreConfig extends Config(
      new WithTSI ++
-      new WithNoGPIO ++
      new WithBootROM ++
      new WithUART ++
      new freechips.rocketchip.subsystem.WithNoMMIOPort ++
--- a/docs/Generators/NVDLA.rst
+++ b/docs/Generators/NVDLA.rst
@@ -0,0 +1,16 @@
+NVDLA
+====================================
+
+`NVDLA <http://nvdla.org/>`_ is an open-source deep learning accelerator developed by NVIDIA.
+The `NVDLA` is attached as a TileLink peripheral so it can be used as a component within the `Rocket Chip SoC generator`.
+The accelerator by itself exposes an AXI memory interface (or two if you use the "Large" configuration), a control interface, and an interrupt line.
+The main way to use the accelerator in Chipyard is to use the `NVDLA SW repository <https://github.com/ucb-bar/nvdla-sw>`_ that was ported to work on FireSim Linux.
+However, you can also use the accelerator in baremetal simulations (refer to ``tests/nvdla.c``).
+
+For more information on both the HW architecture and the SW, please visit their `website <http://nvdla.org/>`_.
+
+NVDLA Software with FireMarshal
+-------------------------------
+
+Located at ``software/nvdla-workload`` is a FireMarshal-based workload to boot Linux with the proper NVDLA drivers.
+Refer to that ``README.md`` for more information on how to run a simulation.
--- a/docs/Generators/TestChipIP.rst
+++ b/docs/Generators/TestChipIP.rst
@@ -84,3 +84,11 @@ output a UART log to a particular file using ``+uartlog=<NAME_OF_FILE>`` during

 By default, this UART Adapter is added to all systems within Chipyard by adding the
 ``WithUART`` and ``WithUARTAdapter`` configs.
+
+SPI Flash Model
+---------------
+
+The SPI flash model is a device that models a simple SPI flash device. It currently
+only supports single read, quad read, single write, and quad write instructions. The
+memory is backed by a file which is provided using ``+spiflash#=<NAME_OF_FILE>``,
+where ``#`` is the SPI flash ID (usually ``0``).
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -28,4 +28,5 @@ so changes to the generators themselves will automatically be used when building
   SiFive-Generators
   SHA3
   Ariane
+   NVDLA

--- a/docs/Simulation/Software-RTL-Simulation.rst
+++ b/docs/Simulation/Software-RTL-Simulation.rst
@@ -49,6 +49,8 @@ Simulating The Default Example
 To compile the example design, run ``make`` in the selected verilator or VCS directory.
 This will elaborate the ``RocketConfig`` in the example project.

+.. Note:: The elaboration of ``RocketConfig`` requires about 6.5 GB of main memory. Otherwise the process will fail with ``make: *** [firrtl_temp] Error 137`` which is most likely related to limited resources. Other configurations might require even more main memory.
+
 An executable called ``simulator-chipyard-RocketConfig`` will be produced.
 This executable is a simulator that has been compiled based on the design that was built.
 You can then use this executable to run any compatible RV64 code.
--- a/docs/Software/Baremetal.rst
+++ b/docs/Software/Baremetal.rst
@@ -0,0 +1,27 @@
+.. _baremetal-programs:
+
+Baremetal RISC-V Programs
+==========================
+
+To build baremetal RISC-V programs to run in simulation, we use the riscv64-unknown-elf cross-compiler and a fork of the libgloss board support package. To build such a program yourself, simply invoke the cross-compiler with the flags "-fno-common -fno-builtin-printf -specs=htif_nano.specs" and the link with the arguments "-static -specs=htif_nano.specs". For instance, if we want to run a "Hello, World" program in baremetal, we could do the following.
+
+.. code:: c
+
+    #include <stdio.h>
+
+    int main(void)
+    {
+        printf("Hello, World!\n");
+        return 0;
+    }
+
+.. code:: bash
+
+    $ riscv64-unknown-elf-gcc -fno-common -fno-builtin-printf -specs=htif_nano.specs -c hello.c
+    $ riscv64-unknown-elf-gcc -static -specs=htif_nano.specs hello.o -o hello.riscv
+    $ spike hello.riscv
+    Hello, World!
+
+For more examples, look at the `tests/ directory <https://github.com/ucb-bar/chipyard/tree/master/tests>`_ in the chipyard repository.
+
+For more information about the libgloss port, take a look at `its README <https://github.com/ucb-bar/libgloss-htif/blob/master/README.md>`_.
--- a/docs/Software/index.rst
+++ b/docs/Software/index.rst
@@ -19,3 +19,4 @@ challenging to modify.

   FireMarshal
   Spike
+   Baremetal
--- a/docs/Tools/Dromajo.rst
+++ b/docs/Tools/Dromajo.rst
@@ -0,0 +1,22 @@
+Dromajo
+===============================
+
+`Dromajo <https://github.com/chipsalliance/dromajo/>`__ is a RV64GC functional simulator designed for co-simulation.
+To use it as a co-simulator, it requires you to pass the committed trace of instructions coming from the core into the tool.
+Within Chipyard, this is done by connecting to the `TracePort`` signals that are piped to the top level of the DUT.
+While the Rocket core does have a `TracePort`, it does not provide the committed write data that Dromajo requires.
+Thus, Dromajo uses the `ExtendedTracePort` only probided by BOOM (BOOM is the only core that supports Dromajo co-simulation).
+An example of a divergence and Dromajo's printout is shown below.
+
+.. code-block:: shell
+
+    [error] EMU PC ffffffe001055d84, DUT PC ffffffe001055d84
+    [error] EMU INSN 14102973, DUT INSN 14102973
+    [error] EMU WDATA 00000000000220d6, DUT WDATA 00000000000220d4
+    [error] EMU MSTATUS a000000a0, DUT MSTATUS 00000000
+    [error] DUT pending exception -1 pending interrupt -1
+
+Dromajo shows the divergence compared to simulation (PC, inst, inst-bits, write data, etc) and also provides the register state on failure.
+It is useful to catch bugs that affect architectural state before a simulation hangs or crashes.
+
+To use Dromajo with BOOM, refer to :ref:`Debugging RTL` section on Dromajo.
--- a/docs/Tools/index.rst
+++ b/docs/Tools/index.rst
@@ -14,4 +14,4 @@ The following pages will introduce them, and how we can use them in order to gen
   Chisel-Testers
   Dsptools
   Barstools
-
+   Dromajo
--- a/docs/_static/css/custom.css
+++ b/docs/_static/css/custom.css
@@ -0,0 +1,6 @@
+.important {
+  font-size: 175%;
+}
+.important p{
+  font-size: 100%;
+}
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -106,6 +106,9 @@ html_theme_options = {
 # relative to this directory. They are copied after the builtin static files,
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']
+html_css_files = [
+        'css/custom.css',
+]

 # Custom sidebar templates, must be a dictionary that maps document names
 # to template names.
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -10,74 +10,8 @@ Welcome to Chipyard's documentation!

 Chipyard is a framework for designing and evaluating full-system hardware using agile teams.
 It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip.
-New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info.
-
-Quick Start
-===============================
-
-System Requirements
-------------------------------------------
-
-Chipyard is developed and tested on Linux-based systems.
-
-.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
-
-.. Warning:: Working under Windows is not recommended.
-
-Setting up the Chipyard Repo
-------------------------------------------
-
-Start by fetching Chipyard's sources. Run:
-
-.. code-block:: shell
-
-    git clone https://github.com/ucb-bar/chipyard.git
-    cd chipyard
-    ./scripts/init-submodules-no-riscv-tools.sh
-
-This will initialize and checkout all of the necessary git submodules.
-
-Installing the RISC-V Tools
-------------------------------------------
-
-We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure.
-This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``.
-To build the toolchains, you should run:
-
-.. code-block:: shell
-
-    ./scripts/build-toolchains.sh
-
-.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above.
-  If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain.
-
-Finally, set up Chipyard's environment variables and put the newly built toolchain on your path:
-
-.. code-block:: shell
-
-    source ./env.sh
-
-What's Next?
-------------------------------------------
-
-This depends on what you are planning to do with Chipyard.
-
-* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions.
-
-* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions.
-
-* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions.
-
-* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions.
-
-* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`.
-
-* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`.
-
-* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions.
-
-* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions.

+.. IMPORTANT:: **New to Chipyard?** Jump to the :ref:`Initial Repository Setup` page for setup instructions.

 Getting Help
 ------------
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,4 +1,4 @@
-Sphinx==1.7.4
+Sphinx==1.8.5
 Pygments==2.2.0
 sphinx-autobuild
 sphinx_rtd_theme==0.2.5b1
--- a/generators/ariane
+++ b/generators/ariane
--- a/generators/boom
+++ b/generators/boom
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -12,7 +12,42 @@ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple}

 import barstools.iocell.chisel._

-case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module))
+case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p)))
+
+/**
+  * Chipyard provides three baseline, top-level reset schemes, set using the
+  * [[GlobalResetSchemeKey]] in a Parameters instance. These are:
+  *
+  * 1) Synchronous: The input coming to the chip is synchronous to the provided
+  *    clocks and will be used without modification as a synchronous reset.
+  *    This is safe only for use in FireSim and SW simulation.
+  *
+  * 2) Asynchronous: The input reset is asynchronous to the input clock, but it
+  *    is caught and synchronized to that clock before it is dissemenated.
+  *    Thus, downsteam modules will be emitted with synchronously reset state
+  *    elements.
+  *
+  * 3) Asynchronous Full: The input reset is asynchronous to the input clock,
+  *    and is used globally as an async reset. Downstream modules will be emitted
+  *    with asynchronously reset state elements.
+  *
+  */
+sealed trait GlobalResetScheme {
+  def pinIsAsync: Boolean
+}
+sealed trait HasAsyncInput { self: GlobalResetScheme =>
+  def pinIsAsync = true
+}
+
+sealed trait HasSyncInput { self: GlobalResetScheme =>
+  def pinIsAsync = false
+}
+
+case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput
+case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput
+case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput
+case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous)
+

 /**
 * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
@@ -26,16 +61,21 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
  // A list of functions to call in the test harness
  val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction]
  // The system clock
+  // These are given so that IOCell can use DataMirror and generate ports with
+  // the right flow (Input/Output)
  val systemClock = Wire(Input(Clock()))
-  // The system reset (synchronous to clock)
-  val systemReset = Wire(Input(Bool()))
+  val systemReset = Wire(Input(Reset()))

  // The system module specified by BuildSystem
-  val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) }
+  val lSystem = p(BuildSystem)(p).suggestName("system")
+  val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) }

  // Call all of the IOBinders and provide them with a default clock and reset
  withClockAndReset(systemClock, systemReset) {
-    val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3
+    // Call each IOBinder on both the lazyModule instance and the module
+    // instance. Generally, an IOBinder PF should only be defined on one, so
+    // this should not lead to two invocations.
+    val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3
    // We ignore _ports for now...
    iocells ++= _iocells.flatten
    harnessFunctions ++= _harnessFunctions.flatten
@@ -45,13 +85,22 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with

 /**
 * A simple clock and reset implementation that punches out clock and reset ports with the same
- * names as the implicit clock and reset for standard Module classes. Reset is synchronous to
- * clock, which may not be a good idea to use for tapeouts.
+ * names as the implicit clock and reset for standard Module classes. Three basic reset schemes 
+ * are provided. See [[GlobalResetScheme]].
 */
 trait HasChipTopSimpleClockAndReset { this: BaseChipTop =>

  val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock"))
-  val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"))
+  val (reset, systemResetIO) = p(GlobalResetSchemeKey) match {
+    case GlobalResetSynchronous  =>
+      IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"))
+    case GlobalResetAsynchronousFull =>
+      IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"), abstractResetAsAsync = true)
+    case GlobalResetAsynchronous =>
+      val asyncResetCore = Wire(Input(AsyncReset()))
+      systemReset := ResetCatchAndSync(systemClock, asyncResetCore.asBool)
+      IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_reset"), abstractResetAsAsync = true)
+  }

  iocells ++= systemClockIO
  iocells ++= systemResetIO
@@ -68,35 +117,5 @@ trait HasChipTopSimpleClockAndReset { this: BaseChipTop =>

 }

-/**
- * Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset
- * can be asynchronous with clock, which is useful for tapeout configs.
- */
-trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop =>
-
-  val asyncResetCore = Wire(Input(Bool()))
-  systemReset := ResetCatchAndSync(systemClock, asyncResetCore)
-
-  val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock"))
-  val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset"))
-
-  iocells ++= systemClockIO
-  iocells ++= asyncResetIO
-
-  // Add a TestHarnessFunction that connects clock and areset
-  harnessFunctions += { (th: TestHarness) => {
-    // Connect clock; it's not done implicitly with RawModule
-    clock := th.clock
-    // Connect reset; it's not done implicitly with RawModule
-    // Note that we need to use dutReset, not harnessReset
-    areset := th.dutReset
-    Nil
-  } }
-
-}
-
 class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p)
  with HasChipTopSimpleClockAndReset
-
-class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p)
-  with HasChipTopSimpleClockAndCaughtReset
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -13,15 +13,16 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 import freechips.rocketchip.util.{AsyncResetReg}

 import boom.common.{BoomTilesKey}
-
+import ariane.{ArianeTilesKey}
 import testchipip._

 import hwacha.{Hwacha}

 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._

-import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset}
+import chipyard.{BuildTop, BuildSystem}

 /**
 * TODO: Why do we need this?
@@ -52,8 +53,10 @@ class WithUART extends Config((site, here, up) => {
    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
 })

-class WithNoGPIO extends Config((site, here, up) => {
-  case PeripheryGPIOKey => Seq()
+class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
+  // Note: the default size matches freedom with the addresses below
+  case PeripherySPIFlashKey => Seq(
+    SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size))
 })

 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -66,10 +69,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 })

 class WithTracegenSystem extends Config((site, here, up) => {
-  case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module)
+  case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p))
 })

-
 class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => {
  case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) =>
    r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length))
@@ -80,12 +82,6 @@ class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here
  case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size)
 })

-
-
-// ------------------
-// Multi-RoCC Support
-// ------------------
-
 /**
 * Map from a hartId to a particular RoCC accelerator
 */
@@ -151,12 +147,8 @@ class WithControlCore extends Config((site, here, up) => {
  case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })

-
-/**
- * Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to
- * the top-level reset, allowing it to be asynchronous with the clock.
- * NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config
- */
-class WithChipTopCaughtReset extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top"))
+class WithTraceIO extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
+  case TracePortKey => Some(TracePortParams())
 })
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -19,11 +19,13 @@ class DigitalTop(implicit p: Parameters) extends System
  with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
  with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
  with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
+  with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
  with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
  with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
  with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget
  with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget
+  with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
 {
  override lazy val module = new DigitalTopModule(this)
 }
@@ -34,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
  with testchipip.CanHavePeripherySerialModuleImp
  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
+  with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
  with icenet.CanHavePeripheryIceNICModuleImp
  with chipyard.example.CanHavePeripheryGCDModuleImp
  with freechips.rocketchip.util.DontTouch
--- a/generators/chipyard/src/main/scala/Generator.scala
+++ b/generators/chipyard/src/main/scala/Generator.scala
@@ -1,40 +1,6 @@
 package chipyard

-import scala.util.Try
+import firrtl.options.{StageMain}
+import chipyard.stage.ChipyardStage

-import chisel3._
-
-import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.util.{GeneratorApp}
-import freechips.rocketchip.system.{TestGeneration}
-
-object Generator extends GeneratorApp {
-  // add unique test suites
-  override def addTestSuites {
-    implicit val p: Parameters = params
-    TestSuiteHelper.addRocketTestSuites
-    TestSuiteHelper.addBoomTestSuites
-    TestSuiteHelper.addArianeTestSuites
-
-    // if hwacha parameter exists then generate its tests
-    // TODO: find a more elegant way to do this. either through
-    // trying to disambiguate BuildRoCC, having a AccelParamsKey,
-    // or having the Accelerator/Tile add its own tests
-    import hwacha.HwachaTestSuites._
-    if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
-      TestGeneration.addSuites(rv64uv.map(_("p")))
-      TestGeneration.addSuites(rv64uv.map(_("vp")))
-      TestGeneration.addSuite(rv64sv("p"))
-      TestGeneration.addSuite(hwachaBmarks)
-    }
-  }
-
-  // specify the name that the generator outputs files as
-  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-
-  // generate files
-  generateFirrtl
-  generateAnno
-  generateTestSuiteMakefrags
-  generateArtefacts
-}
+object Generator extends StageMain(new ChipyardStage)
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -8,10 +8,12 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system.{SimAXIMem}
 import freechips.rocketchip.util._

 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._

 import barstools.iocell.chisel._

@@ -87,10 +89,8 @@ object AddIOCells {
  def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = {
    gpios.zipWithIndex.map({ case (gpio, i) =>
      gpio.pins.zipWithIndex.map({ case (pin, j) =>
-        val g = IO(Analog(1.W))
-        g.suggestName("gpio_${i}_${j}")
-        val iocell = genFn()
-        iocell.suggestName(s"iocell_gpio_${i}_${j}")
+        val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
+        val iocell = genFn().suggestName(s"iocell_gpio_${i}_${j}")
        iocell.io.o := pin.o.oval
        iocell.io.oe := pin.o.oe
        iocell.io.ie := pin.o.ie
@@ -103,7 +103,7 @@ object AddIOCells {

  /**
   * Add IO cells to a SiFive UART devices and name the IO ports.
-   * @param gpios A Seq of UART port bundles
+   * @param uartPins A Seq of UART port bundles
   * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references)
   */
  def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = {
@@ -114,20 +114,62 @@ object AddIOCells {
    }).unzip
  }

+  /**
+   * Add IO cells to a SiFive SPI devices and name the IO ports.
+   * @param spiPins A Seq of SPI port bundles
+   * @param basename The base name for this port (defaults to "spi")
+   * @param genFn A callable function to generate a DigitalGPIOCell module to use
+   * @return Returns a tuple of (A Seq of top-level SPIChipIO IOs; a 2D Seq of IOCell module references)
+   */
+  def spi(spiPins: Seq[SPIPortIO], basename: String = "spi", genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[SPIChipIO], Seq[Seq[IOCell]]) = {
+    spiPins.zipWithIndex.map({ case (s, i) =>
+      val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"${basename}_${i}")
+      val iocellBase = s"iocell_${basename}_${i}"
+
+      // SCK and CS are unidirectional outputs
+      val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"))
+      val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"))
+
+      // DQ are bidirectional, so then need special treatment
+      val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
+        val iocell = genFn().suggestName(s"${iocellBase}_dq_${j}")
+        iocell.io.o := pin.o
+        iocell.io.oe := pin.oe
+        iocell.io.ie := true.B
+        pin.i := iocell.io.i
+        iocell.io.pad <> ana
+        iocell
+      }
+
+      (port, dqIOs ++ csIOs ++ sckIOs)
+    }).unzip
+  }
+
  /**
   * Add IO cells to a debug module and name the IO ports.
-   * @param gpios A PSDIO bundle
+   * @param psd A PSDIO bundle
+   * @param resetctrlOpt An optional ResetCtrlIO bundle
   * @param debugOpt An optional DebugIO bundle
   * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references)
   */
-  def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = {
-    val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd"))
-    val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug")))
-    val debugPortOpt: Option[DebugIO] = optTuple.map(_._1)
-    val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten
+  def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters):
+      (PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = {
+    val (psdPort, psdIOs) = IOCell.generateIOFromSignal(
+      psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+    val debugTuple = debugOpt.map(d =>
+      IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
+    val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1)
+    val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten
    debugPortOpt.foreach(_.suggestName("debug"))
+
+    val resetctrlTuple = resetctrlOpt.map(d =>
+      IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
+    val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1)
+    val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten
+    resetctrlPortOpt.foreach(_.suggestName("resetctrl"))
+
    psdPort.suggestName("psd")
-    (psdPort, debugPortOpt, psdIOs ++ debugIOs)
+    (psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs)
  }

  /**
@@ -160,6 +202,14 @@ class WithUARTAdapter extends OverrideIOBinder({
  }
 })

+class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({
+  (system: HasPeripherySPIFlashModuleImp) => {
+    val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi")
+    val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil }
+    Seq((ports, ioCells2d.flatten, Some(harnessFn)))
+  }
+})
+
 class WithSimBlockDevice extends OverrideIOBinder({
  (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil
 })
@@ -176,29 +226,32 @@ class WithSimNIC extends OverrideIOBinder({
  (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
 })

+// Note: The parameters instance is accessible only through the BaseSubsystem
+// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
+// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
+// accessible to the IOBinder
 // DOC include start: WithSimAXIMem
 class WithSimAXIMem extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil
+  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil
 })
 // DOC include end: WithSimAXIMem

 class WithBlackBoxSimMem extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPortModuleImp) => {
-    (system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) =>
+  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+    (system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) =>
      val memSize = system.p(ExtMem).get.master.size
      val lineSize = system.p(CacheBlockBytes)
-      (io zip node.in).foreach { case (axi4, (_, edge)) =>
-        val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
-        mem.io.axi <> axi4
-        mem.io.clock := system.clock
-        mem.io.reset := system.reset
-      }
-    }; Nil
+      val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
+      mem.io.axi <> io
+      mem.io.clock := system.module.clock
+      mem.io.reset := system.module.reset
+    }
+    Nil
  }
 })

 class WithSimAXIMMIO extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil
+  (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil
 })

 class WithDontTouchPorts extends OverrideIOBinder({
@@ -215,7 +268,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({
 })

 class WithTieOffL2FBusAXI extends OverrideIOBinder({
-  (system: CanHaveSlaveAXI4PortModuleImp) => {
+  (system: CanHaveSlaveAXI4Port with BaseSubsystem) => {
    system.l2_frontend_bus_axi4.foreach(axi => {
      axi.tieoff()
      experimental.DataMirror.directionOf(axi.ar.ready) match {
@@ -235,23 +288,29 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({

 class WithTiedOffDebug extends OverrideIOBinder({
  (system: HasPeripheryDebugModuleImp) => {
-    val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug)
+    val (psdPort, resetctrlOpt, debugPortOpt, ioCells) =
+      AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
    val harnessFn = (th: chipyard.TestHarness) => {
-      Debug.tieoffDebug(debugPortOpt, psdPort)
+      Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p)
      // tieoffDebug doesn't actually tie everything off :/
-      debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
+      debugPortOpt.foreach { d =>
+        d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.clock })
+        d.dmactiveAck := DontCare
+        d.clock := th.clock
+      }
      Nil
    }
-    Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn)))
+    Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn)))
  }
 })

 class WithSimDebug extends OverrideIOBinder({
  (system: HasPeripheryDebugModuleImp) => {
-    val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug)
+    val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) =
+      AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
    val harnessFn = (th: chipyard.TestHarness) => {
      val dtm_success = Wire(Bool())
-      Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p)
+      Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p)
      when (dtm_success) { th.success := true.B }
      th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B)
      Nil
@@ -292,4 +351,12 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({
  }
 })

-}
+class WithSimDromajoBridge extends ComposeIOBinder({
+   (system: CanHaveTraceIOModuleImp) => {
+     system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
+     Nil
+   }
+})
+
+
+} /* end package object */
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -24,6 +24,8 @@ import freechips.rocketchip.amba.axi4._
 import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
 import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}

+import testchipip.{DromajoHelper}
+
 trait HasChipyardTiles extends HasTiles
  with CanHavePeripheryPLIC
  with CanHavePeripheryCLINT
@@ -52,26 +54,20 @@ trait HasChipyardTiles extends HasTiles
  // TODO: investigate why
  val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
    case (param, crossing) => {
-      val (tile, rocketLogicalTree) = param match {
+
+      val tile = param match {
        case r: RocketTileParams => {
-          val t = LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
-          (t, t.rocketLogicalTree)
+          LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
        }
        case b: BoomTileParams => {
-          val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
-          (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
+          LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
        }
        case a: ArianeTileParams => {
-          val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
-          (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
+          LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
        }
      }
      connectMasterPortsToSBus(tile, crossing)
      connectSlavePortsToCBus(tile, crossing)
-
-      def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets)
-      LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree)
-
      connectInterrupts(tile, debugOpt, clintOpt, plicOpt)

      tile
@@ -110,4 +106,8 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule

  // create file with boom params
  ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
+
+  // Generate C header with relevant information for Dromajo
+  // This is included in the `dromajo_params.h` header file
+  DromajoHelper.addArtefacts
 }
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -22,7 +22,6 @@ import freechips.rocketchip.util.{DontTouch}
 * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
 */
 class System(implicit p: Parameters) extends Subsystem
-  with HasHierarchicalBusTopology
  with HasAsyncExtInterrupts
  with CanHaveMasterAXI4MemPort
  with CanHaveMasterAXI4MMIOPort
@@ -38,8 +37,5 @@ class System(implicit p: Parameters) extends Subsystem
 class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
  with HasRTCModuleImp
  with HasExtInterruptsModuleImp
-  with CanHaveMasterAXI4MemPortModuleImp
-  with CanHaveMasterAXI4MMIOPortModuleImp
-  with CanHaveSlaveAXI4PortModuleImp
  with HasPeripheryBootROMModuleImp
  with DontTouch
--- a/generators/chipyard/src/main/scala/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/TestHarness.scala
@@ -25,9 +25,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
  val dut = p(BuildTop)(p)
  io.success := false.B

-  // dutReset can be overridden via a harnessFunction, but by default it is just reset
-  val dutReset = Wire(Bool())
-  dutReset := reset
+  // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset
+  val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset)

  dut.harnessFunctions.foreach(_(this))

--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -5,8 +5,7 @@ import scala.collection.mutable.{LinkedHashSet}
 import freechips.rocketchip.subsystem.{RocketTilesKey}
 import freechips.rocketchip.tile.{XLen}
 import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.util.{GeneratorApp}
-import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
+import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}

 import boom.common.{BoomTilesKey}
 import ariane.{ArianeTilesKey}
@@ -56,10 +55,13 @@ object RegressionTestSuites
 /**
 * Helper functions to add BOOM or Rocket tests
 */
-object TestSuiteHelper
+class TestSuiteHelper
 {
  import freechips.rocketchip.system.DefaultTestSuites._
  import RegressionTestSuites._
+  val suites = collection.mutable.ListMap[String, RocketTestSuite]()
+  def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }
+  def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }

  /**
  * Add BOOM tests (asm, bmark, regression)
@@ -72,33 +74,33 @@ object TestSuiteHelper
      val env = if (vm) List("p","v") else List("p")
      coreParams.fpu foreach { case cfg =>
        if (xlen == 32) {
-          TestGeneration.addSuites(env.map(rv32uf))
+          addSuites(env.map(rv32uf))
          if (cfg.fLen >= 64) {
-            TestGeneration.addSuites(env.map(rv32ud))
+            addSuites(env.map(rv32ud))
          }
        } else if (cfg.fLen >= 64) {
-          TestGeneration.addSuites(env.map(rv64ud))
-          TestGeneration.addSuites(env.map(rv64uf))
-          TestGeneration.addSuite(rv32udBenchmarks)
+          addSuites(env.map(rv64ud))
+          addSuites(env.map(rv64uf))
+          addSuite(rv32udBenchmarks)
        }
      }
      if (coreParams.useAtomics) {
        if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
-          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
        } else {
-          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
        }
      }
-      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
      val (rvi, rvu) =
        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
        else            ((if (vm) rv32i else rv32pi), rv32u)

-      TestGeneration.addSuites(rvi.map(_("p")))
-      TestGeneration.addSuites(rvu.map(_("p")))
-      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-      TestGeneration.addSuite(benchmarks)
-      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+      addSuites(rvi.map(_("p")))
+      addSuites(rvu.map(_("p")))
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      addSuite(benchmarks)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
    }
  }

@@ -113,31 +115,31 @@ object TestSuiteHelper
      val env = if (vm) List("p","v") else List("p")
      coreParams.fpu foreach { case cfg =>
        if (xlen == 32) {
-          TestGeneration.addSuites(env.map(rv32uf))
+          addSuites(env.map(rv32uf))
          if (cfg.fLen >= 64)
-            TestGeneration.addSuites(env.map(rv32ud))
+            addSuites(env.map(rv32ud))
        } else {
-          TestGeneration.addSuite(rv32udBenchmarks)
-          TestGeneration.addSuites(env.map(rv64uf))
+          addSuite(rv32udBenchmarks)
+          addSuites(env.map(rv64uf))
          if (cfg.fLen >= 64)
-            TestGeneration.addSuites(env.map(rv64ud))
+            addSuites(env.map(rv64ud))
        }
      }
      if (coreParams.useAtomics) {
        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
        else
-          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
      }
-      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
      val (rvi, rvu) =
        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
        else            ((if (vm) rv32i else rv32pi), rv32u)

-      TestGeneration.addSuites(rvi.map(_("p")))
-      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-      TestGeneration.addSuite(benchmarks)
-      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+      addSuites(rvi.map(_("p")))
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      addSuite(benchmarks)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
    }
  }

@@ -152,32 +154,31 @@ object TestSuiteHelper
      val env = if (vm) List("p","v") else List("p")
      coreParams.fpu foreach { case cfg =>
        if (xlen == 32) {
-          TestGeneration.addSuites(env.map(rv32uf))
+          addSuites(env.map(rv32uf))
          if (cfg.fLen >= 64)
-            TestGeneration.addSuites(env.map(rv32ud))
+            addSuites(env.map(rv32ud))
        } else {
-          TestGeneration.addSuite(rv32udBenchmarks)
-          TestGeneration.addSuites(env.map(rv64uf))
+          addSuite(rv32udBenchmarks)
+          addSuites(env.map(rv64uf))
          if (cfg.fLen >= 64)
-            TestGeneration.addSuites(env.map(rv64ud))
+            addSuites(env.map(rv64ud))
        }
      }
      if (coreParams.useAtomics) {
        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
        else
-          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
      }
-      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
      val (rvi, rvu) =
        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
        else            ((if (vm) rv32i else rv32pi), rv32u)

-      TestGeneration.addSuites(rvi.map(_("p")))
-      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-      TestGeneration.addSuite(benchmarks)
-      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+      addSuites(rvi.map(_("p")))
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      addSuite(benchmarks)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
    }
  }
-
 }
--- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala
@@ -15,7 +15,6 @@ class ArianeConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
  new chipyard.config.WithBootROM ++                             // use default bootrom
  new chipyard.config.WithUART ++                                // add a UART
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
@@ -23,6 +22,7 @@ class ArianeConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
  new ariane.WithNArianeCores(1) ++                              // single Ariane core
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system

 class dmiArianeConfig extends Config(
@@ -31,7 +31,6 @@ class dmiArianeConfig extends Config(
  new chipyard.iobinders.WithSimAXIMem ++
  new chipyard.iobinders.WithTiedOffSerial ++
  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
@@ -39,4 +38,5 @@ class dmiArianeConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new ariane.WithNArianeCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
--- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -13,7 +13,6 @@ class SmallBoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
  new chipyard.config.WithBootROM ++                             // use default bootrom
  new chipyard.config.WithUART ++                                // add a UART
  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
@@ -23,6 +22,7 @@ class SmallBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
  new boom.common.WithSmallBooms ++                              // small boom config
  new boom.common.WithNBoomCores(1) ++                           // single-core boom
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system

 class MediumBoomConfig extends Config(
@@ -32,7 +32,6 @@ class MediumBoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -42,6 +41,7 @@ class MediumBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new boom.common.WithMediumBooms ++                              // medium boom config
  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class LargeBoomConfig extends Config(
@@ -51,7 +51,6 @@ class LargeBoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -61,6 +60,7 @@ class LargeBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new boom.common.WithLargeBooms ++                              // large boom config
  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class MegaBoomConfig extends Config(
@@ -70,7 +70,6 @@ class MegaBoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -80,6 +79,7 @@ class MegaBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new boom.common.WithMegaBooms ++                              // mega boom config
  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class DualSmallBoomConfig extends Config(
@@ -89,7 +89,6 @@ class DualSmallBoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -99,6 +98,7 @@ class DualSmallBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new boom.common.WithSmallBooms ++
  new boom.common.WithNBoomCores(2) ++                         // 2 boom cores
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class SmallRV32BoomConfig extends Config(
@@ -108,7 +108,6 @@ class SmallRV32BoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -120,6 +119,7 @@ class SmallRV32BoomConfig extends Config(
  new boom.common.WithBoomRV32 ++                          // rv32 (32bit)
  new boom.common.WithSmallBooms ++
  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class HwachaLargeBoomConfig extends Config(
@@ -129,7 +129,6 @@ class HwachaLargeBoomConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -140,6 +139,7 @@ class HwachaLargeBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new boom.common.WithLargeBooms ++
  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class LoopbackNICLargeBoomConfig extends Config(
@@ -151,7 +151,6 @@ class LoopbackNICLargeBoomConfig extends Config(
  new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
  new testchipip.WithTSI ++
  new icenet.WithIceNIC ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -161,5 +160,27 @@ class LoopbackNICLargeBoomConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new boom.common.WithLargeBooms ++
  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DromajoBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithSimDromajoBridge ++                 // attach Dromajo
+  new testchipip.WithTSI ++
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

--- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
@@ -13,7 +13,6 @@ class LargeBoomAndRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
  new chipyard.config.WithBootROM ++                             // use default bootrom
  new chipyard.config.WithUART ++                                // add a UART
  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
@@ -25,6 +24,7 @@ class LargeBoomAndRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system

 // DOC include start: BoomAndRocketWithHwacha
@@ -35,7 +35,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -48,6 +47,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: BoomAndRocketWithHwacha

@@ -58,7 +58,6 @@ class DualLargeBoomAndRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -70,6 +69,7 @@ class DualLargeBoomAndRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 // DOC include start: DualBoomAndRocketOneHwacha
@@ -81,7 +81,6 @@ class LargeBoomAndHwachaRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
@@ -95,6 +94,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DualBoomAndRocketOneHwacha

@@ -107,7 +107,6 @@ class LargeBoomAndRV32RocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -120,6 +119,7 @@ class LargeBoomAndRV32RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)


@@ -131,7 +131,6 @@ class DualLargeBoomAndDualRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -143,6 +142,7 @@ class DualLargeBoomAndDualRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // 2 rocket cores
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DualBoomAndRocket

@@ -153,7 +153,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithControlCore ++  // add small control core to last hartid
@@ -166,5 +165,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -13,7 +13,6 @@ class RocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
  new chipyard.config.WithBootROM ++                             // use default bootrom
  new chipyard.config.WithUART ++                                // add a UART
  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
@@ -22,6 +21,7 @@ class RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system

 class HwachaRocketConfig extends Config(
@@ -31,7 +31,6 @@ class HwachaRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -41,6 +40,7 @@ class HwachaRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 // DOC include start: GemminiRocketConfig
@@ -51,7 +51,6 @@ class GemminiRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -61,6 +60,7 @@ class GemminiRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GemminiRocketConfig

@@ -71,7 +71,6 @@ class RoccRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -81,6 +80,7 @@ class RoccRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 // DOC include start: JtagRocket
@@ -91,7 +91,6 @@ class jtagRocketConfig extends Config(
  new chipyard.iobinders.WithSimDebug ++    // add SimJtag and SimSerial, use both to drive sim
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -101,6 +100,7 @@ class jtagRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: JtagRocket

@@ -111,7 +111,6 @@ class dmiRocketConfig extends Config(
  new chipyard.iobinders.WithBlackBoxSimMem ++
  new chipyard.iobinders.WithTiedOffSerial ++
  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -120,6 +119,7 @@ class dmiRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DmiRocket

@@ -131,7 +131,6 @@ class GCDTLRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -141,6 +140,7 @@ class GCDTLRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GCDTLRocketConfig

@@ -153,7 +153,6 @@ class GCDAXI4BlackBoxRocketConfig extends Config(
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
  new chipyard.config.WithUART ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithL2TLBs(1024) ++
  new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++          // Use GCD blackboxed verilog, connect by AXI4->Tilelink
@@ -162,9 +161,50 @@ class GCDAXI4BlackBoxRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig

+class LargeSPIFlashROMRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithSimSPIFlashModel(true) ++      // add the SPI flash model in the harness (read-only)
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithSPIFlash ++                       // add the SPI flash controller
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class SmallSPIFlashRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithSimSPIFlashModel(false) ++     // add the SPI flash model in the harness (writeable)
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithSPIFlash(0x100000) ++             // add the SPI flash controller (1 MiB)
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+
 class SimBlockDeviceRocketConfig extends Config(
  new chipyard.iobinders.WithUARTAdapter ++
  new chipyard.iobinders.WithTieOffInterrupts ++
@@ -174,7 +214,6 @@ class SimBlockDeviceRocketConfig extends Config(
  new chipyard.iobinders.WithSimBlockDevice ++             // drive block-device IOs with SimBlockDevice
  new testchipip.WithTSI ++
  new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -183,6 +222,7 @@ class SimBlockDeviceRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class BlockDeviceModelRocketConfig extends Config(
@@ -194,7 +234,6 @@ class BlockDeviceModelRocketConfig extends Config(
  new chipyard.iobinders.WithBlockDeviceModel ++           // drive block-device IOs with a BlockDeviceModel
  new testchipip.WithTSI ++
  new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -203,6 +242,7 @@ class BlockDeviceModelRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 // DOC include start: GPIORocketConfig
@@ -223,6 +263,7 @@ class GPIORocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GPIORocketConfig

@@ -235,13 +276,13 @@ class QuadRocketConfig extends Config(
  new testchipip.WithTSI ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithL2TLBs(1024) ++
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
  new freechips.rocketchip.subsystem.WithNoSlavePort ++
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(4) ++   // quad-core (4 RocketTiles)
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class RV32RocketConfig extends Config(
@@ -251,7 +292,6 @@ class RV32RocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
@@ -260,6 +300,7 @@ class RV32RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class GB1MemoryRocketConfig extends Config(
@@ -269,7 +310,6 @@ class GB1MemoryRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -279,6 +319,7 @@ class GB1MemoryRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 // DOC include start: Sha3Rocket
@@ -289,7 +330,6 @@ class Sha3RocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -299,6 +339,7 @@ class Sha3RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: Sha3Rocket

@@ -310,7 +351,6 @@ class InitZeroRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -320,6 +360,7 @@ class InitZeroRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: InitZeroRocketConfig

@@ -332,7 +373,6 @@ class LoopbackNICRocketConfig extends Config(
  new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
  new testchipip.WithTSI ++
  new icenet.WithIceNIC ++                                         // add an IceNIC
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -341,6 +381,7 @@ class LoopbackNICRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 // DOC include start: scratchpadrocket
@@ -351,7 +392,6 @@ class ScratchpadRocketConfig extends Config(
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
  new testchipip.WithBackingScratchpad ++              // add backing scratchpad
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -361,6 +401,7 @@ class ScratchpadRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: scratchpadrocket

@@ -372,7 +413,6 @@ class RingSystemBusRocketConfig extends Config(
  new chipyard.iobinders.WithTiedOffDebug ++
  new chipyard.iobinders.WithSimSerial ++
  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithUART ++
  new chipyard.config.WithL2TLBs(1024) ++
@@ -382,6 +422,7 @@ class RingSystemBusRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: RingSystemBusRocket

@@ -396,3 +437,41 @@ class UIntTestFIRRocketConfig extends Config (
  new RocketConfig
 )
 // DOC include end: FIRRocketConfig
+
+class SmallNVDLARocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class LargeNVDLARocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -8,6 +8,7 @@ class TraceGenConfig extends Config(
  new chipyard.iobinders.WithTraceGenSuccessBinder ++
  new chipyard.config.WithTracegenSystem ++
  new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class NonBlockingTraceGenConfig extends Config(
@@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config(
  new chipyard.iobinders.WithTraceGenSuccessBinder ++
  new chipyard.config.WithTracegenSystem ++
  new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class BoomTraceGenConfig extends Config(
@@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config(
  new chipyard.config.WithTracegenSystem ++
  new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class NonBlockingTraceGenL2Config extends Config(
@@ -31,6 +34,7 @@ class NonBlockingTraceGenL2Config extends Config(
  new chipyard.config.WithTracegenSystem ++
  new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)

 class NonBlockingTraceGenL2RingConfig extends Config(
@@ -40,4 +44,5 @@ class NonBlockingTraceGenL2RingConfig extends Config(
  new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
  new testchipip.WithRingSystemBus ++
  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig)
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -29,7 +29,6 @@ class TutorialStarterConfig extends Config(
  // Config fragments below this line affect hardware generation
  // of the Top
  new testchipip.WithTSI ++                  // Add a TSI (Test Serial Interface)  widget to bring-up the core
-  new chipyard.config.WithNoGPIO ++          // Disable GPIOs.
  new chipyard.config.WithBootROM ++         // Use the Chipyard BootROM
  new chipyard.config.WithRenumberHarts ++   // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op
  new chipyard.config.WithUART ++            // Add a UART
@@ -51,6 +50,7 @@ class TutorialStarterConfig extends Config(
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
  new freechips.rocketchip.subsystem.WithNoSlavePort ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
  // BaseConfig configures "bare" rocketchip system
  new freechips.rocketchip.system.BaseConfig
 )
@@ -65,7 +65,6 @@ class TutorialMMIOConfig extends Config(
  new chipyard.iobinders.WithSimSerial ++

  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithRenumberHarts ++
  new chipyard.config.WithUART ++
@@ -81,6 +80,7 @@ class TutorialMMIOConfig extends Config(
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
  new freechips.rocketchip.subsystem.WithNoSlavePort ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig
 )

@@ -93,7 +93,6 @@ class TutorialSha3Config extends Config(
  new chipyard.iobinders.WithSimSerial ++

  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithRenumberHarts ++
  new chipyard.config.WithUART ++
@@ -107,6 +106,7 @@ class TutorialSha3Config extends Config(
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
  new freechips.rocketchip.subsystem.WithNoSlavePort ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig
 )

@@ -119,7 +119,6 @@ class TutorialSha3BlackBoxConfig extends Config(
  new chipyard.iobinders.WithSimSerial ++

  new testchipip.WithTSI ++
-  new chipyard.config.WithNoGPIO ++
  new chipyard.config.WithBootROM ++
  new chipyard.config.WithRenumberHarts ++
  new chipyard.config.WithUART ++
@@ -134,5 +133,6 @@ class TutorialSha3BlackBoxConfig extends Config(
  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
  new freechips.rocketchip.subsystem.WithNoSlavePort ++
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
  new freechips.rocketchip.system.BaseConfig
 )
--- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala
+++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import freechips.rocketchip.stage.ConfigsAnnotation
+import firrtl.options.{HasShellOptions, ShellOption}
+
+/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format  */
+private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "legacy-configs",
+      toAnnotationSeq = a => {
+        val split = a.split('.')
+        val packageName = split.init.mkString(".")
+        val configs     = split.last.split("_")
+        Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } ))
+      },
+      helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).",
+      shortOption = Some("LC")
+    )
+  )
+}
+
--- a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala
+++ b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala
@@ -0,0 +1,15 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import firrtl.options.Shell
+
+trait ChipyardCli { this: Shell =>
+
+  parser.note("Chipyard Generator Options")
+  Seq(
+    UnderscoreDelimitedConfigsAnnotation
+  )
+    .foreach(_.addOptions(parser))
+}
--- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala
+++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import chisel3.stage.{ChiselCli, ChiselStage}
+import firrtl.options.PhaseManager.PhaseDependency
+import firrtl.options.{Phase, PreservesAll, Shell}
+import firrtl.stage.FirrtlCli
+import freechips.rocketchip.stage.RocketChipCli
+import freechips.rocketchip.system.RocketChipStage
+
+import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
+import firrtl.options.phases.DeletedWrapper
+
+class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
+  override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
+  override val targets: Seq[PhaseDependency] = Seq(
+    Dependency[freechips.rocketchip.stage.phases.Checks],
+    Dependency[freechips.rocketchip.stage.phases.TransformAnnotations],
+    Dependency[freechips.rocketchip.stage.phases.PreElaboration],
+    Dependency[chisel3.stage.phases.Checks],
+    Dependency[chisel3.stage.phases.Elaborate],
+    Dependency[freechips.rocketchip.stage.phases.GenerateROMs],
+    Dependency[chisel3.stage.phases.AddImplicitOutputFile],
+    Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
+    Dependency[chisel3.stage.phases.MaybeAspectPhase],
+    Dependency[chisel3.stage.phases.Emitter],
+    Dependency[chisel3.stage.phases.Convert],
+    Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
+    Dependency[freechips.rocketchip.stage.phases.AddDefaultTests],
+    Dependency[chipyard.stage.phases.AddDefaultTests],
+    Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
+    Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
+  )
+}
--- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
+++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
@@ -0,0 +1,67 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage.phases
+
+import scala.util.Try
+import scala.collection.mutable
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3.stage.phases.Elaborate
+import firrtl.AnnotationSeq
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{Phase, PreservesAll, Dependency}
+import firrtl.options.Viewer.view
+import freechips.rocketchip.stage.RocketChipOptions
+import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
+import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
+import freechips.rocketchip.util.HasRocketChipStageUtils
+import freechips.rocketchip.tile.XLen
+
+import chipyard.TestSuiteHelper
+
+class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
+  // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
+  // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). 
+  override val prerequisites = Seq(
+    Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
+    Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])
+  override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])
+
+  private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
+    val annotations = mutable.ArrayBuffer[Annotation]()
+    val suiteHelper = new TestSuiteHelper
+    // Use Xlen as a proxy for detecting if we are a processor-like target
+    // The underlying test suites expect this field to be defined
+    if (p.lift(XLen).nonEmpty) {
+      suiteHelper.addRocketTestSuites
+      suiteHelper.addBoomTestSuites
+      suiteHelper.addArianeTestSuites
+    }
+
+    // if hwacha parameter exists then generate its tests
+    // TODO: find a more elegant way to do this. either through
+    // trying to disambiguate BuildRoCC, having a AccelParamsKey,
+    // or having the Accelerator/Tile add its own tests
+    import hwacha.HwachaTestSuites._
+    if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
+      suiteHelper.addSuites(rv64uv.map(_("p")))
+      suiteHelper.addSuites(rv64uv.map(_("vp")))
+      suiteHelper.addSuite(rv64sv("p"))
+      suiteHelper.addSuite(hwachaBmarks)
+      annotations += CustomMakefragSnippet(
+        "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
+    }
+    RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
+  }
+
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val (testSuiteAnnos, oAnnos) = annotations.partition {
+      case RocketTestSuiteAnnotation(_)  => true
+      case o => false
+    }
+    implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance
+    addTestSuiteAnnotations ++ oAnnos
+  }
+}
--- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
+++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
@@ -0,0 +1,49 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage.phases
+
+import scala.collection.mutable
+
+import firrtl.AnnotationSeq
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency}
+import firrtl.options.Viewer.view
+import freechips.rocketchip.stage.RocketChipOptions
+import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
+import freechips.rocketchip.system.TestGeneration
+import freechips.rocketchip.util.HasRocketChipStageUtils
+
+trait MakefragSnippet { self: Annotation =>
+  def toMakefrag: String
+}
+
+case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
+
+/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
+class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
+
+  // Our annotations tend not to be serializable, but are not marked as such.
+  override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
+                                   Dependency[chipyard.stage.phases.AddDefaultTests])
+
+  override def transform(annotations: AnnotationSeq): AnnotationSeq = {
+    val targetDir = view[StageOptions](annotations).targetDir
+    val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d"
+
+    val makefragBuilder = new mutable.StringBuilder()
+    val outputAnnotations = annotations.flatMap {
+      case RocketTestSuiteAnnotation(tests) =>
+        // Unfortunately the gen method of TestGeneration is rocketchip package
+        // private, so we either have to copy code in or use the stateful form
+        TestGeneration.addSuites(tests)
+        None
+      case a: MakefragSnippet =>
+        makefragBuilder :+ ("\n" + a.toMakefrag)
+        None
+      case a => Some(a)
+    }
+    writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)
+    outputAnnotations
+  }
+}
--- a/generators/chipyard/src/main/scala/unittest/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala
@@ -0,0 +1,9 @@
+package chipyard.unittest
+
+import chisel3._
+import freechips.rocketchip.config.Parameters
+
+class TestHarness(implicit val p: Parameters) extends Module {
+  val io = IO(new Bundle { val success = Output(Bool()) })
+  io.success := Module(new UnitTestSuite).io.finished
+}
--- a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
+++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
@@ -0,0 +1,8 @@
+package chipyard.unittest
+
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}
+
+class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {
+  ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
+}
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -8,12 +8,12 @@ import chisel3.experimental.annotate
 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp}
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem}
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}

-import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
+import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
 import icenet.CanHavePeripheryIceNICModuleImp

 import junctions.{NastiKey, NastiParameters}
@@ -27,7 +27,8 @@ import ariane.ArianeTile
 import boom.common.{BoomTile}

 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
-import chipyard.HasChipyardTilesModuleImp
+import chipyard.{HasChipyardTilesModuleImp}
+import testchipip.{CanHaveTraceIOModuleImp}

 object MainMemoryConsts {
  val regionNamePrefix = "MainMemory"
@@ -56,30 +57,36 @@ class WithBlockDeviceBridge extends OverrideIOBinder({


 class WithFASEDBridge extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPortModuleImp) => {
+  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
    implicit val p = system.p
-    (system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) =>
-      (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
-        val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
-                                       axi4Bundle.ar.bits.addr.getWidth,
-                                       axi4Bundle.ar.bits.id.getWidth)
-        FASEDBridge(system.clock, axi4Bundle, system.reset.toBool,
-          CompleteConfig(p(firesim.configs.MemModelKey),
-                         nastiKey,
-                         Some(AXI4EdgeSummary(edge)),
-                         Some(MainMemoryConsts.globalName)))
-      })
+    (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
+      val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
+                                     axi4.ar.bits.addr.getWidth,
+                                     axi4.ar.bits.id.getWidth)
+      FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
+        CompleteConfig(p(firesim.configs.MemModelKey),
+                       nastiKey,
+                       Some(AXI4EdgeSummary(edge)),
+                       Some(MainMemoryConsts.globalName)))
    })
    Nil
  }
 })

-class WithTracerVBridge extends OverrideIOBinder({
+class WithTracerVBridge extends ComposeIOBinder({
  (system: CanHaveTraceIOModuleImp) =>
    system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
 })


+
+class WithDromajoBridge extends ComposeIOBinder({
+  (system: CanHaveTraceIOModuleImp) => {
+    system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
+  }
+})
+
+
 class WithTraceGenBridge extends OverrideIOBinder({
  (system: HasTraceGenTilesModuleImp) =>
    GroundTestBridge(system.clock, system.success)(system.p); Nil
@@ -116,9 +123,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({

 class WithTiedOffSystemDebug extends OverrideIOBinder({
  (system: HasPeripheryDebugModuleImp) => {
-    Debug.tieoffDebug(system.debug, system.psd)
+    Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
    // tieoffDebug doesn't actually tie everything off :/
-    system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
+    system.debug.foreach { d =>
+      d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
+      d.dmactiveAck := DontCare
+    }
    Nil
  }
 })
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -29,19 +29,31 @@ object NodeIdx {
 }

 class FireSim(implicit val p: Parameters) extends RawModule {
+  freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
  val clockBridge = Module(new RationalClockBridge)
  val clock = clockBridge.io.clocks.head
  val reset = WireInit(false.B)
  withClockAndReset(clock, reset) {
    // Instantiate multiple instances of the DUT to implement supernode
-    val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
+    val targets = Seq.fill(p(NumNodes)) {
+      // It's not a RC bump without some hacks...
+      // Copy the AsyncClockGroupsKey to generate a fresh node on each
+      // instantiation of the dut, otherwise the initial instance will be
+      // reused across each node
+      import freechips.rocketchip.subsystem.AsyncClockGroupsKey
+      val lazyModule = p(BuildSystem)(p.alterPartial({
+        case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
+      }))
+      (lazyModule, Module(lazyModule.module))
+    }
+
    val peekPokeBridge = PeekPokeBridge(clock, reset)
    // A Seq of partial functions that will instantiate the right bridge only
-    // if that Mixin trait is present in the target's class instance
+    // if that Mixin trait is present in the target's LazyModule class instance
    //
    // Apply each partial function to each DUT instance
-    for ((target) <- targets) {
-      p(IOBinders).values.map(_(target))
+    for ((lazyModule, module) <- targets) {
+      p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
      NodeIdx.increment()
    }
  }
--- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala
+++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala
@@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config
 class HalfRateUncore extends WithSingleRationalTileDomain(2,1)

 class WithFiresimMulticlockTop extends Config((site, here, up) => {
-  case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module)
+  case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system")
 })

 // Complete Config
@@ -79,25 +79,30 @@ class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop
  override lazy val module = new FiresimMulticlockTopModule(this)
 }

+
 class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp

 // Harness Definition
 class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
+  freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
  val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
  val refClock = clockBridge.io.clocks.head
  val reset = WireInit(false.B)
  withClockAndReset(refClock, reset) {
    // Instantiate multiple instances of the DUT to implement supernode
-    val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
+    val targets = Seq.fill(p(NumNodes)) {
+      val lazyModule = p(BuildSystem)(p)
+      (lazyModule, Module(lazyModule.module))
+    }
    val peekPokeBridge = PeekPokeBridge(refClock, reset)
    // A Seq of partial functions that will instantiate the right bridge only
    // if that Mixin trait is present in the target's class instance
    //
    // Apply each partial function to each DUT instance
-    for ((target) <- targets) {
-      p(IOBinders).values.map(_(target))
+    for ((lazyModule, module) <- targets) {
+      p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
    }
-    targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
+    targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks })
  }
 }

--- a/generators/firechip/src/main/scala/Generator.scala
+++ b/generators/firechip/src/main/scala/Generator.scala
@@ -1,79 +0,0 @@
-//See LICENSE for license details.
-
-package firesim.firesim
-
-import java.io.{File, FileWriter}
-
-import chisel3.RawModule
-import chisel3.internal.firrtl.{Circuit, Port}
-
-import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
-import freechips.rocketchip.devices.debug.DebugIO
-import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
-import freechips.rocketchip.system.DefaultTestSuites._
-import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.subsystem.RocketTilesKey
-import freechips.rocketchip.tile.XLen
-
-import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
-
-import scala.util.Try
-
-import chipyard.TestSuiteHelper
-
-trait HasTestSuites {
-  def addTestSuites(targetName: String, params: Parameters) {
-    TestSuiteHelper.addRocketTestSuites(params)
-    TestSuiteHelper.addBoomTestSuites(params)
-    TestSuiteHelper.addArianeTestSuites(params)
-    TestGeneration.addSuite(FastBlockdevTests)
-    TestGeneration.addSuite(SlowBlockdevTests)
-    if (!targetName.contains("NoNIC"))
-      TestGeneration.addSuite(NICLoopbackTests)
-
-    import hwacha.HwachaTestSuites._
-    if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
-      TestGeneration.addSuites(rv64uv.map(_("p")))
-      TestGeneration.addSuites(rv64uv.map(_("vp")))
-      TestGeneration.addSuite(rv64sv("p"))
-      TestGeneration.addSuite(hwachaBmarks)
-    }
-  }
-}
-
-// Mixed into an App or into a TestSuite
-trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites {
-  /** Output software test Makefrags, which provide targets for integration testing. */
-  def generateTestSuiteMakefrags {
-    addTestSuites(names.topModuleClass, targetParams)
-    writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites
-  }
-
-  // Output miscellaneous files produced as a side-effect of elaboration
-  def generateArtefacts {
-    ElaborationArtefacts.files.foreach { case (extension, contents) =>
-      writeOutputFile(s"${longName}.${extension}", contents ())
-    }
-  }
-}
-
-object FireSimGenerator extends App with IsFireSimGeneratorLike {
-  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-  lazy val generatorArgs = GeneratorArgs(args)
-  lazy val genDir = new File(names.targetDir)
-  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different
-  // JsonProtocol to properly write out the annotations. Fix once the generated are unified
-  elaborate
-  generateTestSuiteMakefrags
-  generateArtefacts
-}
-
-// For now, provide a separate generator app when not specifically building for FireSim
-object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
-  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-  generateFirrtl
-  generateAnno
-  generateTestSuiteMakefrags
-  generateArtefacts
-}
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -41,17 +41,15 @@ class WithBootROM extends Config((site, here, up) => {
 })

 class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => {
-  case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
+  case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
 })

-
 class WithPerfCounters extends Config((site, here, up) => {
  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
    core = tile.core.copy(nPerfCounters = 29)
  ))
 })

-
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
@@ -63,7 +61,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
  case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
 })

-
 // FASED Config Aliases. This to enable config generation via "_" concatenation
 // which requires that all config classes be defined in the same package
 class DDR3FRFCFS extends FRFCFS16GBQuadRank
@@ -71,14 +68,9 @@ class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB

 class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)

-
-
-// Enables tracing on all cores
-class WithTraceIO extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
-  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
-  case TracePortKey => Some(TracePortParams())
-})
+// Adds a small/large NVDLA to the system
+class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large")
+class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")


 // Tweaks that are generally applied to all firesim configs
@@ -92,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
  // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
  new WithoutTLMonitors ++
  // Optional: Adds IO to attach tracerV bridges
-  new WithTraceIO ++
+  new chipyard.config.WithTraceIO ++
  // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
  // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
@@ -143,7 +135,6 @@ class FireSimLargeBoomConfig extends Config(
  new WithFireSimConfigTweaks ++
  new chipyard.LargeBoomConfig)

-
 //********************************************************************
 // Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
 //********************************************************************
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -6,44 +6,34 @@ import java.io.File
 import scala.concurrent.{Future, Await, ExecutionContext}
 import scala.sys.process.{stringSeqToProcess, ProcessLogger}
 import scala.io.Source
+import org.scalatest.Suites

 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite}
 import freechips.rocketchip.system.TestGeneration._
 import freechips.rocketchip.system.DefaultTestSuites._

-import firesim.util.GeneratorArgs
-
 abstract class FireSimTestSuite(
    topModuleClass: String,
    targetConfigs: String,
    platformConfigs: String,
    N: Int = 8
-  ) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
+  ) extends firesim.TestSuiteCommon {
  import scala.concurrent.duration._
  import ExecutionContext.Implicits.global

-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  val topModuleProject = "firesim.firesim"

-  lazy val generatorArgs = GeneratorArgs(
-    midasFlowKind = "midas",
-    targetDir = "generated-src",
-    topModuleProject = "firesim.firesim",
-    topModuleClass = topModuleClass,
-    targetConfigProject = "firesim.firesim",
-    targetConfigs = targetConfigs ++ "_WithScalaTestFeatures",
-    platformConfigProject = "firesim.firesim",
-    platformConfigs = platformConfigs)
-
-  // From HasFireSimGeneratorUtilities
-  // For the firesim utilities to use the same directory as the test suite
-  override lazy val testDir = genDir
+  val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs

  // From TestSuiteCommon
-  val targetTuple = generatorArgs.tupleName
-  val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
-                           s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
-                           s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
+  val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs"
+  val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}",
+                           s"TARGET_CONFIG=${targetConfigs}",
+                           s"PLATFORM_CONFIG=${platformConfigs}")
+
+  override lazy val genDir  = new File(firesimDir, s"generated-src/${chipyardLongName}")
+

  def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
    make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
@@ -61,12 +51,6 @@ abstract class FireSimTestSuite(
    }
  }

-  //def runReplay(backend: String, replayBackend: String, name: String) = {
-  //  val dir = (new File(outDir, backend)).getAbsolutePath
-  //  (Seq("make", s"replay-$replayBackend",
-  //       s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).!
-  //}
-
  def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) {
    // compile emulators
    behavior of s"${suite.makeTargetName} running on $backend"
@@ -83,20 +67,6 @@ abstract class FireSimTestSuite(
      results.flatten foreach { case (name, exitcode) =>
        it should s"pass $name" in { assert(exitcode == 0) }
      }
-      //replayBackends foreach { replayBackend =>
-      //  if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) {
-      //    assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs
-      //    suite.names foreach { name =>
-      //      it should s"replay $name in $replayBackend" in {
-      //        assert(runReplay(backend, replayBackend, s"$name$postfix") == 0)
-      //      }
-      //    }
-      //  } else {
-      //    suite.names foreach { name =>
-      //      ignore should s"replay $name in $backend"
-      //    }
-      //  }
-      //}
    } else {
      ignore should s"pass $backend"
    }
@@ -127,62 +97,24 @@ abstract class FireSimTestSuite(
  }

  clean
-  mkdirs
-  elaborate
-  generateTestSuiteMakefrags
  runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
-  //diffTracelog("rv64ui-p-simple.out")
  runSuite("verilator")(benchmarks)
-  runSuite("verilator")(FastBlockdevTests)
 }

 class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config")
-class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
-class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
-  runSuite("verilator")(NICLoopbackTests)
-}
-// Disabled until RAM optimizations re-enabled in multiclock
-//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams")
-//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams")
-
+class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config")
+class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config")
 // Multiclock tests
 class RocketMulticlockF1Tests extends FireSimTestSuite(
  "FireSimMulticlockPOC",
  "FireSimQuadRocketMulticlockConfig",
  "WithSynthAsserts_BaseF1Config")

-// Jerry broke these -- damn it Jerry.
-//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
-//    extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
-//  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-//
-//  lazy val generatorArgs = GeneratorArgs(
-//    midasFlowKind = "midas",
-//    targetDir = "generated-src",
-//    topModuleProject = "firesim.firesim",
-//    topModuleClass = "FireSimTraceGen",
-//    targetConfigProject = "firesim.firesim",
-//    targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
-//    platformConfigProject = "firesim.firesim",
-//    platformConfigs = platformConfig)
-//
-//  // From HasFireSimGeneratorUtilities
-//  // For the firesim utilities to use the same directory as the test suite
-//  override lazy val testDir = genDir
-//
-//  // From TestSuiteCommon
-//  val targetTuple = generatorArgs.tupleName
-//  val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
-//                           s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
-//                           s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
-//
-//  it should "pass" in {
-//    assert(make("fsim-tracegen") == 0)
-//  }
-//}
-//
-//class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
-//  "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
-//
-//class FireSimL2TraceGenTest extends FireSimTraceGenTest(
-//  "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")
+class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
+
+// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
+class CITests extends Suites(
+  new RocketF1Tests,
+  new BoomF1Tests,
+  new RocketNICF1Tests,
+  new RocketMulticlockF1Tests)
--- a/generators/hwacha
+++ b/generators/hwacha
--- a/generators/icenet
+++ b/generators/icenet
--- a/generators/nvdla
+++ b/generators/nvdla
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
--- a/generators/sifive-blocks
+++ b/generators/sifive-blocks
--- a/generators/sifive-cache
+++ b/generators/sifive-cache
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -41,7 +41,6 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp {

 class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
    with HasTraceGenTiles
-    with HasHierarchicalBusTopology
    with CanHaveMasterAXI4MemPort {
  override lazy val module = new TraceGenSystemModuleImp(this)
 }
@@ -49,4 +48,3 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
 class TraceGenSystemModuleImp(outer: TraceGenSystem)
  extends BaseSubsystemModuleImp(outer)
  with HasTraceGenTilesModuleImp
-  with CanHaveMasterAXI4MemPortModuleImp
--- a/generators/tracegen/src/main/scala/Tile.scala
+++ b/generators/tracegen/src/main/scala/Tile.scala
@@ -165,8 +165,15 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
  io.lsu.rob_pnr_idx := rob_tail
  io.lsu.commit_load_at_rob_head := false.B

-  io.lsu.brinfo := DontCare
-  io.lsu.brinfo.valid := false.B
+  io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.exu.BrUpdateMasks)
+  io.lsu.brupdate.b2.uop := DontCare
+  io.lsu.brupdate.b2.mispredict := false.B
+  io.lsu.brupdate.b2.taken := false.B
+  io.lsu.brupdate.b2.cfi_type := 0.U
+  io.lsu.brupdate.b2.pc_sel := 0.U
+  io.lsu.brupdate.b2.jalr_target := 0.U
+  io.lsu.brupdate.b2.target_offset := 0.S(2.W)
+
  io.lsu.rob_head_idx := rob_head


--- a/generators/utilities/src/main/resources/csrc/emulator.cc
+++ b/generators/utilities/src/main/resources/csrc/emulator.cc
@@ -38,8 +38,8 @@ extern remote_bitbang_t * jtag;
 extern int dramsim;

 static uint64_t trace_count = 0;
-bool verbose;
-bool done_reset;
+bool verbose = false;
+bool done_reset = false;

 void handle_sigterm(int sig)
 {
@@ -282,8 +282,12 @@ done_processing:
  signal(SIGTERM, handle_sigterm);

  bool dump;
+  // start reset off low so a rising edge triggers async reset
+  tile->reset = 0;
+  tile->clock = 0;
+  tile->eval();
  // reset for several cycles to handle pipelined reset
-  for (int i = 0; i < 10; i++) {
+  for (int i = 0; i < 100; i++) {
    tile->reset = 1;
    tile->clock = 0;
    tile->eval();
--- a/project/build.properties
+++ b/project/build.properties
@@ -1 +1 @@
-sbt.version=1.2.8
+sbt.version=1.3.2
--- a/project/plugins.sbt
+++ b/project/plugins.sbt
@@ -1,6 +1,6 @@
-resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns)
+resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns)
 resolvers += Classpaths.sbtPluginReleases
-resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
+resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven"

 addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")
 addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
@@ -14,5 +14,6 @@ addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
 addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
 addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3")
 addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4")
+addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1")

 libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1"
--- a/scripts/build-toolchains.sh
+++ b/scripts/build-toolchains.sh
@@ -130,10 +130,15 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow

 SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu

+# make Dromajo
+git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src
+make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src
+
 cd "$RDIR"

 # create specific env.sh
 {
+    echo "# auto-generated by build-toolchains.sh"
    echo "export CHIPYARD_TOOLCHAIN_SOURCED=1"
    echo "export RISCV=$(printf '%q' "$RISCV")"
    echo "export PATH=\${RISCV}/bin:\${PATH}"
@@ -141,5 +146,6 @@ cd "$RDIR"
 } > env-$TOOLCHAIN.sh

 # create general env.sh
+echo "# line auto-generated by build-toolchains.sh" >> env.sh
 echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/env-$TOOLCHAIN.sh" >> env.sh
 echo "Toolchain Build Complete!"
--- a/scripts/centos-req.sh
+++ b/scripts/centos-req.sh
@@ -22,5 +22,5 @@ sudo yum install -y dtc
 # install verilator
 git clone http://git.veripool.org/git/verilator
 cd verilator
-git checkout v4.028
+git checkout v4.034
 autoconf && ./configure && make -j16 && sudo make install
--- a/scripts/init-submodules-no-riscv-tools-nolog.sh
+++ b/scripts/init-submodules-no-riscv-tools-nolog.sh
@@ -59,11 +59,6 @@ git submodule update --init generators/sha3
 git config --unset submodule.sims/firesim.update
 # Minimal non-recursive clone to initialize sbt dependencies
 git submodule update --init sims/firesim
-(
-    cd sims/firesim
-    # Initialize dependencies for MIDAS-level RTL simulation
-    git submodule update --init sim/midas
-)
 git config submodule.sims/firesim.update none

 # Only shallow clone needed for basic SW tests
@@ -73,4 +68,5 @@ git submodule update --init software/firemarshal
 if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then
  echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml
 fi
+echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> $RDIR/env.sh
 echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh
--- a/scripts/insert-includes.py
+++ b/scripts/insert-includes.py
@@ -0,0 +1,51 @@
+#!/usr/bin/python
+
+# replaces a `include with the full include file
+#
+# args
+# $1 - file to remove includes from
+# $2 - file to write output to
+# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs)
+#      includes are found relative to this path
+#      this is equivalent to something like +incdir+
+
+import sys
+import re
+import os
+
+inVlog = sys.argv[1]
+outVlog = sys.argv[2]
+print("[INFO] Replaces includes from: " + str(inVlog))
+
+if inVlog == outVlog:
+    sys.exit("[ERROR] The input and output file cannot be the same.")
+
+# add directories to search list
+incDirs = sys.argv[3:]
+print("[INFO] Searching following dirs for includes: " + str(incDirs))
+
+# open file
+with open(inVlog, 'r') as inFile:
+    with open(outVlog, 'w') as outFile:
+        # for each include found, search through all dirs and replace if found, error if not
+        for num, line in enumerate(inFile, 1):
+            match = re.match(r"^ *`include +\"(.*)\"", line)
+            if match:
+                # search for include and replace
+                found = False
+                for d in incDirs:
+                    potentialIncFileName = d + "/" + match.group(1)
+                    if os.path.exists(potentialIncFileName):
+                        found = True
+                        with open(potentialIncFileName, 'r') as incFile:
+                            for iline in incFile:
+                                outFile.write(iline)
+                        break
+
+                # must find something to include with
+                if not found:
+                    sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
+            else:
+                outFile.write(line)
+
+print("[INFO] Success. Writing output to: " + str(outVlog))
--- a/scripts/tutorial-patches/RocketConfigs.scala.patch
+++ b/scripts/tutorial-patches/RocketConfigs.scala.patch
@@ -1,8 +1,8 @@
 diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-index bc1dab6..1d84129 100644
+index f29c580..0bd36ca 100644
 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
 +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-@@ -293,7 +293,7 @@ class Sha3RocketConfig extends Config(
+@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config(
   new chipyard.config.WithBootROM ++
   new chipyard.config.WithUART ++
   new chipyard.config.WithL2TLBs(1024) ++
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,17 +1,17 @@
 diff --git a/build.sbt b/build.sbt
-index a633066..3df8b74 100644
+index 0c4581f..ff0597c 100644
 --- a/build.sbt
 +++ b/build.sbt
-@@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
+@@ -128,7 +128,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/"))
 
 lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
-     gemmini, icenet, tracegen, ariane)
+     gemmini, icenet, tracegen, ariane, nvdla)
   .settings(commonSettings)
 
-@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane"))
+@@ -155,9 +155,9 @@ lazy val ariane = (project in file("generators/ariane"))
   .dependsOn(rocketchip)
   .settings(commonSettings)
 
--- a/scripts/ubuntu-req.sh
+++ b/scripts/ubuntu-req.sh
@@ -23,5 +23,5 @@ sudo apt-get install -y device-tree-compiler
 # install verilator
 git clone http://git.veripool.org/git/verilator
 cd verilator
-git checkout v4.028
+git checkout v4.034
 autoconf && ./configure && make -j16 && sudo make install
--- a/sims/firesim
+++ b/sims/firesim
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -55,18 +55,16 @@ VCS_CC_OPTS = \

 VCS_NONCC_OPTS = \
 	+lint=all,noVCDE,noONGS,noUI \
-	-error=PCWM-L \
-	-timescale=1ns/10ps \
+	-timescale=1ns/1ps \
 	-quiet \
 	-q \
 	+rad \
-	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
 	-error=noZMMCM \
-	-assert svaext \
-	-sverilog \
-	+libext+.v \
+	-error=PCWM-L \
+	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	+incdir+$(build_dir) \
 	-f $(sim_common_files) \
 	$(sim_vsrcs)
@@ -102,6 +100,10 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)

+$(output_dir)/none.vpd: $(sim_debug)
+	mkdir -p $(output_dir)
+	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log)
+
 #########################################################################################
 # general cleanup rule
 #########################################################################################
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -72,7 +72,6 @@ ARIANE_VERILATOR_FLAGS = \
 	--unroll-count 256 \
 	-Werror-PINMISSING \
 	-Werror-IMPLICIT \
-	-Wno-fatal \
 	-Wno-PINCONNECTEMPTY \
 	-Wno-ASSIGNDLY \
 	-Wno-DECLFILENAME \
@@ -86,11 +85,16 @@ ARIANE_VERILATOR_FLAGS = \
 CHIPYARD_VERILATOR_FLAGS = \
 	--assert

+# Use --timescale to approximate timescale behavior of pre-4.034
+TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
 VERILATOR_NONCC_OPTS = \
+	$(TIMESCALE_OPTS) \
 	--top-module $(VLOG_MODEL) \
+	-Wno-fatal \
 	$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
 	--output-split 10000 \
 	--output-split-cfuncs 100 \
+	--max-num-width 1048576 \
 	-f $(sim_common_files) \
 	$(sim_vsrcs)

@@ -116,14 +120,14 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 # build makefile fragment that builds the verilator sim rules
 #########################################################################################
 $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
-	rm -rf $(build_dir)/$(long_name)
-	mkdir -p $(build_dir)/$(long_name)
+	rm -rf $(model_dir)
+	mkdir -p $(model_dir)
 	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
 	touch $@

 $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
-	rm -rf $(build_dir)/$(long_name)
-	mkdir -p $(build_dir)/$(long_name).debug
+	rm -rf $(model_dir_debug)
+	mkdir -p $(model_dir_debug)
 	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
 	touch $@

@@ -145,6 +149,12 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	vcd2vpd $@.vcd $@ > /dev/null &
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)

+$(output_dir)/none.vpd: $(sim_debug)
+	mkdir -p $(output_dir)
+	rm -f $@.vcd && mkfifo $@.vcd
+	vcd2vpd $@.vcd $@ > /dev/null &
+	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log)
+
 #########################################################################################
 # general cleanup rule
 #########################################################################################
--- a/software/firemarshal
+++ b/software/firemarshal
--- a/software/nvdla-workload
+++ b/software/nvdla-workload
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -1,4 +1,5 @@
 *.o
 *.riscv
 *.dump
+*.img
 libgloss/
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -5,12 +5,16 @@ LDFLAGS= -static

 include libgloss.mk

-PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd passthrough fir
+PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
+           passthrough fir nvdla spiflashread spiflashwrite
+
+spiflash.img: spiflash.py
+	python3 $<

 .DEFAULT_GOAL := default

 .PHONY: default
-default: $(addsuffix .riscv,$(PROGRAMS))
+default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img

 .PHONY: dumps
 dumps: $(addsuffix .dump,$(PROGRAMS))
@@ -18,7 +22,7 @@ dumps: $(addsuffix .dump,$(PROGRAMS))
 %.o: %.S
 	$(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@

-%.o: %.c mmio.h
+%.o: %.c mmio.h spiflash.h
 	$(GCC) $(CFLAGS) -c $< -o $@

 %.riscv: %.o $(libgloss)
--- a/tests/nvdla.c
+++ b/tests/nvdla.c
@@ -0,0 +1,468 @@
+#include <stdint.h>
+
+#include "nvdla.h"
+#include "mmio.h"
+#include <riscv-pk/encoding.h>
+
+#define NVDLA_BASE 0x10040000
+#define reg_write(addr,val) reg_write32(NVDLA_BASE+addr,val)
+#define reg_read(addr) reg_read32(NVDLA_BASE+addr)
+
+int main(void)
+{
+    //----------## Layer:CDP_0: cross layer dependency, begin----------
+    //----------## Layer:CDP_0: cross layer dependency, end----------
+    //----------## Layer:CDP_0: set producer pointer, begin----------
+    reg_write(CDP_S_POINTER_0, 0);
+    reg_write(CDP_RDMA_S_POINTER_0, 0);
+    //----------## Layer:CDP_0: set producer pointer, end----------
+    //----------## Layer:CDP_0: LUT programming, begin----------
+    reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x30000);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x41);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x42);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x43);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x44);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x45);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x46);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x47);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x48);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x49);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x50);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x51);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x52);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x53);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x54);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x55);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x56);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x57);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x58);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x59);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x60);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x61);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x62);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x63);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x64);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x65);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x66);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x67);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x68);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x69);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x70);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x71);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x72);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x73);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x74);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x75);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x76);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x77);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x78);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x79);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x80);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x81);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x82);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x83);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x84);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x85);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x86);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x87);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x88);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x89);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x90);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x91);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x92);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x93);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x94);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x95);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x96);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x97);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x98);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x99);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaa);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xab);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xac);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xad);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xae);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaf);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xba);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbc);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbd);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbe);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbf);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xca);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcc);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcd);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xce);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcf);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xda);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdc);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdd);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xde);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdf);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xea);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xeb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xec);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xed);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xee);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xef);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfa);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfc);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfd);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfe);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xff);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x100);
+    reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x20000);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f);
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40);
+    reg_write(CDP_S_LUT_LE_START_LOW_0, 0x0);
+    // CDP_S_LUT_LE_START_LOW_0.LUT_LE_START_LOW:0x0
+    reg_write(CDP_S_LUT_LO_END_LOW_0, 0x100);
+    // CDP_S_LUT_LO_END_LOW_0.LUT_LO_END_LOW:0x100
+    reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x0);
+    // CDP_S_LUT_ACCESS_CFG_0.LUT_ACCESS_TYPE:READ : 0x0
+    // CDP_S_LUT_ACCESS_CFG_0.LUT_TABLE_ID:LE : 0x0
+    // CDP_S_LUT_ACCESS_CFG_0.LUT_ADDR:0x0
+    reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0);
+    // CDP_S_LUT_ACCESS_DATA_0.LUT_DATA:0x0
+    reg_write(CDP_S_LUT_LE_START_HIGH_0, 0x0);
+    // CDP_S_LUT_LE_START_HIGH_0.LUT_LE_START_HIGH:0x0
+    reg_write(CDP_S_LUT_LO_END_HIGH_0, 0x0);
+    // CDP_S_LUT_LO_END_HIGH_0.LUT_LO_END_HIGH:0x0
+    reg_write(CDP_S_LUT_CFG_0, 0x1);
+    // CDP_S_LUT_CFG_0.LUT_UFLOW_PRIORITY:LE : 0x0
+    // CDP_S_LUT_CFG_0.LUT_OFLOW_PRIORITY:LE : 0x0
+    // CDP_S_LUT_CFG_0.LUT_HYBRID_PRIORITY:LE : 0x0
+    // CDP_S_LUT_CFG_0.LUT_LE_FUNCTION:LINEAR : 0x1
+    reg_write(CDP_S_LUT_LE_SLOPE_SHIFT_0, 0x0);
+    // CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_OFLOW_SHIFT:0x0
+    // CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_UFLOW_SHIFT:0x0
+    reg_write(CDP_S_LUT_LE_SLOPE_SCALE_0, 0x0);
+    // CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_UFLOW_SCALE:0x0
+    // CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_OFLOW_SCALE:0x0
+    reg_write(CDP_S_LUT_INFO_0, 0x0);
+    // CDP_S_LUT_INFO_0.LUT_LE_INDEX_SELECT:0x0
+    // CDP_S_LUT_INFO_0.LUT_LE_INDEX_OFFSET:0x0
+    // CDP_S_LUT_INFO_0.LUT_LO_INDEX_SELECT:0x0
+    reg_write(CDP_S_LUT_LE_END_LOW_0, 0x40);
+    // CDP_S_LUT_LE_END_LOW_0.LUT_LE_END_LOW:0x40
+    reg_write(CDP_S_LUT_LO_SLOPE_SCALE_0, 0x0);
+    // CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_OFLOW_SCALE:0x0
+    // CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_UFLOW_SCALE:0x0
+    reg_write(CDP_S_LUT_LE_END_HIGH_0, 0x0);
+    // CDP_S_LUT_LE_END_HIGH_0.LUT_LE_END_HIGH:0x0
+    reg_write(CDP_S_LUT_LO_START_HIGH_0, 0x0);
+    // CDP_S_LUT_LO_START_HIGH_0.LUT_LO_START_HIGH:0x0
+    reg_write(CDP_S_LUT_LO_START_LOW_0, 0x0);
+    // CDP_S_LUT_LO_START_LOW_0.LUT_LO_START_LOW:0x0
+    reg_write(CDP_S_LUT_LO_SLOPE_SHIFT_0, 0x0);
+    // CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_UFLOW_SHIFT:0x0
+    // CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_OFLOW_SHIFT:0x0
+    //----------## Layer:CDP_0: LUT programming, end----------
+    //----------## Layer:CDP_0: configuraion, begin----------
+    reg_write(CDP_D_DATOUT_OFFSET_0, 0x80);
+    // CDP_D_DATOUT_OFFSET_0.DATOUT_OFFSET:0x80
+    reg_write(CDP_D_DST_SURFACE_STRIDE_0, 0x800);
+    // CDP_D_DST_SURFACE_STRIDE_0.DST_SURFACE_STRIDE:0x40
+    reg_write(CDP_RDMA_D_SRC_BASE_ADDR_LOW_0, 0x90000000);
+    // CDP_RDMA_D_SRC_BASE_ADDR_LOW_0.SRC_BASE_ADDR_LOW:0x4000000
+    reg_write(CDP_D_DST_DMA_CFG_0, 0x1);
+    // CDP_D_DST_DMA_CFG_0.DST_RAM_TYPE:MC : 0x1
+    reg_write(CDP_RDMA_D_DATA_CUBE_WIDTH_0, 0x7);
+    // CDP_RDMA_D_DATA_CUBE_WIDTH_0.WIDTH:0x7
+    reg_write(CDP_RDMA_D_DATA_FORMAT_0, 0x0);
+    // CDP_RDMA_D_DATA_FORMAT_0.INPUT_DATA:INT8 : 0x0
+    reg_write(CDP_D_DATIN_SCALE_0, 0x1);
+    // CDP_D_DATIN_SCALE_0.DATIN_SCALE:0x1
+    reg_write(CDP_D_DATOUT_SHIFTER_0, 0x0);
+    // CDP_D_DATOUT_SHIFTER_0.DATOUT_SHIFTER:0x0
+    reg_write(CDP_D_CYA_0, 0x0);
+    // CDP_D_CYA_0.CYA:0x0
+    reg_write(CDP_RDMA_D_PERF_ENABLE_0, 0x0);
+    // CDP_RDMA_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0
+    reg_write(CDP_D_LRN_CFG_0, 0x0);
+    // CDP_D_LRN_CFG_0.NORMALZ_LEN:LEN3 : 0x0
+    reg_write(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, 0x1f);
+    // CDP_RDMA_D_DATA_CUBE_CHANNEL_0.CHANNEL:0x1f
+    reg_write(CDP_D_DATA_FORMAT_0, 0x0);
+    // CDP_D_DATA_FORMAT_0.INPUT_DATA_TYPE:INT8 : 0x0
+    reg_write(CDP_D_DATIN_SHIFTER_0, 0x0);
+    // CDP_D_DATIN_SHIFTER_0.DATIN_SHIFTER:0x0
+    reg_write(CDP_D_PERF_ENABLE_0, 0x0);
+    // CDP_D_PERF_ENABLE_0.LUT_EN:DISABLE : 0x0
+    // CDP_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0
+    reg_write(CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0, 0x0);
+    // CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0.SRC_BASE_ADDR_HIGH:0x0
+    reg_write(CDP_D_DST_BASE_ADDR_HIGH_0, 0x0);
+    // CDP_D_DST_BASE_ADDR_HIGH_0.DST_BASE_ADDR_HIGH:0x0
+    reg_write(CDP_RDMA_D_SRC_DMA_CFG_0, 0x1);
+    // CDP_RDMA_D_SRC_DMA_CFG_0.SRC_RAM_TYPE:MC : 0x1
+    reg_write(CDP_D_DATOUT_SCALE_0, 0x1);
+    // CDP_D_DATOUT_SCALE_0.DATOUT_SCALE:0x1
+    reg_write(CDP_D_DATIN_OFFSET_0, 0x80);
+    // CDP_D_DATIN_OFFSET_0.DATIN_OFFSET:0x80
+    reg_write(CDP_D_NAN_FLUSH_TO_ZERO_0, 0x0);
+    // CDP_D_NAN_FLUSH_TO_ZERO_0.NAN_TO_ZERO:DISABLE : 0x0
+    reg_write(CDP_D_FUNC_BYPASS_0, 0x3);
+    // CDP_D_FUNC_BYPASS_0.SQSUM_BYPASS:ENABLE : 0x1
+    // CDP_D_FUNC_BYPASS_0.MUL_BYPASS:ENABLE : 0x1
+    reg_write(CDP_D_DST_BASE_ADDR_LOW_0, 0x90080000);
+    // CDP_D_DST_BASE_ADDR_LOW_0.DST_BASE_ADDR_LOW:0x4004000
+    reg_write(CDP_RDMA_D_CYA_0, 0x0);
+    // CDP_RDMA_D_CYA_0.CYA:0x0
+    reg_write(CDP_RDMA_D_SRC_SURFACE_STRIDE_0, 0x800);
+    // CDP_RDMA_D_SRC_SURFACE_STRIDE_0.SRC_SURFACE_STRIDE:0x40
+    reg_write(CDP_D_DST_LINE_STRIDE_0, 0x100);
+    // CDP_D_DST_LINE_STRIDE_0.DST_LINE_STRIDE:0x8
+    reg_write(CDP_RDMA_D_SRC_LINE_STRIDE_0, 0x100);
+    // CDP_RDMA_D_SRC_LINE_STRIDE_0.SRC_LINE_STRIDE:0x8
+    reg_write(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, 0x7);
+    // CDP_RDMA_D_DATA_CUBE_HEIGHT_0.HEIGHT:0x7
+    //----------## Layer:CDP_0: configuraion, end----------
+    //----------## Layer:CDP_0: operation enable, begin----------
+    //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, begin --
+    reg_write(CDP_RDMA_D_OP_ENABLE_0,0x1);
+    //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, end   --
+    //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, begin --
+    reg_write(CDP_D_OP_ENABLE_0,0x1);
+    //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, end   --
+    //----------## Layer:CDP_0: operation enable, end----------
+
+    register uint64_t cycle1 = rdcycle();
+
+    for (register int idx = 0; idx < 32767; idx++) {
+        if (reg_read(GLB_S_INTR_STATUS_0) != 0)
+            break;
+    }
+
+    uint64_t cycle2 = rdcycle();
+    printf("cycle1: %lu, cycle2: %lu, diff: %lu\n", cycle1, cycle2, cycle2 - cycle1 );
+
+    return 0;
+}
--- a/tests/nvdla.h
+++ b/tests/nvdla.h
--- a/tests/spiflash.h
+++ b/tests/spiflash.h
@@ -0,0 +1,174 @@
+#ifndef __SPIFLASH_H__
+#define __SPIFLASH_H__
+
+// These are configuration-dependent, but for the unit test we'll use the example config
+#define SPIFLASH_BASE_MEM 0x20000000
+#define SPIFLASH_BASE_MEM_SIZE 0x10000000
+
+#define SPIFLASH_BASE_CTRL 0x10040000
+// Only defining the registers we use; there are more
+// Software control
+#define SPIFLASH_OFFS_CSMODE 0x18
+#define SPIFLASH_OFFS_FMT 0x40
+#define SPIFLASH_OFFS_TXDATA 0x48
+#define SPIFLASH_OFFS_RXDATA 0x4c
+// Hardware state machine control
+#define SPIFLASH_OFFS_FLASH_EN 0x60
+#define SPIFLASH_OFFS_FFMT 0x64
+
+// chip select modes
+#define CSMODE_AUTO 0
+#define CSMODE_HOLD 2
+#define CSMODE_OFF 3
+
+// SPI flash protocol settings
+#define SPIFLASH_PROTO_SINGLE 0
+#define SPIFLASH_PROTO_DUAL 1
+#define SPIFLASH_PROTO_QUAD 2
+
+// SPI flash IO settings
+#define SPIFLASH_IODIR_RX 0
+#define SPIFLASH_IODIR_TX 1
+
+// SPI flash endianness settings
+#define SPIFLASH_ENDIAN_MSB 0
+#define SPIFLASH_ENDIAN_LSB 1
+
+static uint8_t test_data[] = {0x13,0x37,0x00,0xff,0xaa,0x55,0xfa,0xce,0x0f,0xf0,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef};
+static uint8_t test_len = 16;
+
+typedef union
+{
+	struct {
+		unsigned int proto : 2;
+		unsigned int endian : 1;
+		unsigned int iodir : 1;
+		unsigned int : 12;
+		unsigned int len : 4;
+		unsigned int : 12;
+	} fields;
+	uint32_t bits;
+} spi_fmt;
+
+typedef union
+{
+	struct {
+		unsigned int cmd_en : 1;
+		unsigned int addr_len : 3;
+		unsigned int pad_cnt : 4;
+		unsigned int cmd_proto : 2;
+		unsigned int addr_proto : 2;
+		unsigned int data_proto : 2;
+		unsigned int : 2;
+		unsigned int cmd_code : 8;
+		unsigned int pad_code : 8;
+	} fields;
+	uint32_t bits;
+} spiflash_ffmt;
+
+// send something to the SPI TX
+void spi_data_write(uint8_t data)
+{
+	while (reg_read32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA) >= 0x80000000);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA, (uint32_t)data);
+}
+
+// configure the hardware flash controller
+void configure_spiflash(spiflash_ffmt data)
+{
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FFMT, data.bits);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
+}
+
+// write some data to the flash using software (there is no hardware write controller)
+void write_spiflash(uint8_t *data, uint32_t len, uint32_t addr, uint8_t cmd, uint8_t abytes, uint8_t aproto, uint8_t dproto)
+{
+
+	spi_fmt fmt;
+	fmt.fields.proto = SPIFLASH_PROTO_SINGLE;
+	fmt.fields.endian = SPIFLASH_ENDIAN_MSB;
+	fmt.fields.iodir = SPIFLASH_IODIR_TX;
+	fmt.fields.len = 8;
+
+	uint32_t i;
+
+	// Need to be out of flash mode
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
+
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_HOLD);
+
+	spi_data_write(cmd);
+
+	// need to wait a bit to flush the tx queue before changing fmt
+	for(i = 0; i < 0x100; i++) asm volatile ("nop");
+
+	fmt.fields.proto = aproto;
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
+
+	for (i = abytes; i > 0; i--)
+	{
+		spi_data_write((uint8_t)(addr >> (i*8-8)));
+	}
+
+	// need to wait a bit to flush the tx queue before changing fmt
+	for(i = 0; i < 0x100; i++) asm volatile ("nop");
+
+	fmt.fields.proto = dproto;
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
+
+	for (i = 0; i < len; i++)
+	{
+		spi_data_write(data[i]);
+	}
+
+	// need to wait a bit to flush the tx queue before deasserting CS
+	for(i = 0; i < 0x100; i++) asm volatile ("nop");
+
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_OFF);
+
+	// go back into flash read mode
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
+
+}
+
+// test that a large chunk of memory contains (0xdeadbeef - address) or 0
+int test_spiflash(uint32_t start, uint32_t size, uint8_t zero)
+{
+	uint32_t i;
+
+	for (i = start; i < (start + size); i += 4)
+	{
+		uint32_t data = reg_read32(SPIFLASH_BASE_MEM + i);
+		uint32_t check = 0;
+		if (!zero) check = 0xdeadbeef - i;
+		if(data != check)
+		{
+			printf("Error reading address 0x%08x from SPI flash. Got 0x%08x, expected 0x%08x.\n", i, data, check);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+// this is a variant of test_spiflash that only tests a small array of values
+int check_write(uint8_t *check, uint32_t len, uint32_t addr)
+{
+	uint32_t i;
+	for (i = 0; i < len; i += 4)
+	{
+		uint32_t data = reg_read32(SPIFLASH_BASE_MEM + addr + i);
+		uint32_t check32 = ((uint32_t *)check)[i/4];
+		if(check32 != data)
+		{
+			printf("Error reading address 0x%08x from SPI flash. Got 0x%02x, expected 0x%02x.\n", i + addr, data, check32);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+#endif /* __SPIFLASH_H__ */
--- a/tests/spiflash.py
+++ b/tests/spiflash.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python3
+
+# Generates a binary file that the SPI test uses
+
+outfile = "spiflash.img"
+
+with open(outfile, 'wb') as f:
+    for i in range(0,0x100000,4):
+        check = 0xdeadbeef - i
+        f.write(check.to_bytes(4,'little'))
+
--- a/tests/spiflashread.c
+++ b/tests/spiflashread.c
@@ -0,0 +1,77 @@
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "mmio.h"
+#include "spiflash.h"
+
+int main(void)
+{
+	spiflash_ffmt ffmt;
+	ffmt.fields.cmd_en = 1;
+	ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model
+	ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow
+	ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands
+	ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.cmd_code = 0x13; // Slow read 4 byte
+	ffmt.fields.pad_code = 0x00; // Not used by our model
+
+	printf("Testing SPI flash command 0x13...\n");
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x03...\n");
+	ffmt.fields.cmd_code = 0x03; // Slow read 3 byte address
+	ffmt.fields.addr_len = 3; // 3 byte address
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x0B...\n");
+	ffmt.fields.cmd_code = 0x0B; // Fast read 3 byte address
+	ffmt.fields.pad_cnt = 8; // Needs to be 8 for fast read
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x1000, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x0C...\n");
+	ffmt.fields.cmd_code = 0x0C; // Fast read 4 byte address
+	ffmt.fields.addr_len = 4; // 4 byte address
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x2340, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x6C...\n");
+	ffmt.fields.cmd_code = 0x6C; // Fast read 4 byte address, quad data
+	ffmt.fields.data_proto = SPIFLASH_PROTO_QUAD; // Quad data
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x410c, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x6B...\n");
+	ffmt.fields.cmd_code = 0x6B; // Fast read 3 byte address, quad data
+	ffmt.fields.addr_len = 3;
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x5ff8, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0xEB...\n");
+	ffmt.fields.cmd_code = 0xEB; // Fast read 3 byte address, quad data, quad addr
+	ffmt.fields.addr_proto = SPIFLASH_PROTO_QUAD;
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x7c04, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0xEC...\n");
+	ffmt.fields.cmd_code = 0xEC; // Fast read 4 byte address, quad data, quad addr
+	ffmt.fields.addr_len = 4;
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x9000, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash extended range...\n");
+	// The provided memory image is only 1MiB, but the model has 16MiB of addressable space
+	// This should return 0
+	if (test_spiflash(0x100000, 0x100, 1)) return 1;
+
+	// This write should do nothing, so we can just re-test the first test
+	printf("Testing that the SPI is not writable...\n");
+	write_spiflash(test_data, test_len, 0x0, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	return 0;
+
+}
--- a/tests/spiflashwrite.c
+++ b/tests/spiflashwrite.c
@@ -0,0 +1,55 @@
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "mmio.h"
+#include "spiflash.h"
+
+int main(void)
+{
+	spiflash_ffmt ffmt;
+	ffmt.fields.cmd_en = 1;
+	ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model
+	ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow
+	ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands
+	ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.cmd_code = 0x13; // Slow read 4 byte
+	ffmt.fields.pad_code = 0x00; // Not used by our model
+
+	// Test that we can read
+	printf("Testing SPI flash command 0x13...\n");
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	// 0x02: 3 byte addr, single/single
+	printf("Testing SPI flash command 0x02...\n");
+	write_spiflash(test_data, test_len, 0x200, 0x02, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE);
+	if (check_write(test_data, test_len, 0x200)) return 1;
+
+	// 0x32: 3 byte addr, single/quad
+	printf("Testing SPI flash command 0x32...\n");
+	write_spiflash(test_data, test_len, 0x300, 0x32, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x300)) return 1;
+
+	// 0x38: 3 byte addr, quad/quad
+	printf("Testing SPI flash command 0x38...\n");
+	write_spiflash(test_data, test_len, 0x400, 0x38, 3, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x400)) return 1;
+
+	// 0x12: 4 byte addr, single/single
+	printf("Testing SPI flash command 0x12...\n");
+	write_spiflash(test_data, test_len, 0x500, 0x12, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE);
+	if (check_write(test_data, test_len, 0x500)) return 1;
+
+	// 0x34: 4 byte addr, single/quad
+	printf("Testing SPI flash command 0x34...\n");
+	write_spiflash(test_data, test_len, 0x600, 0x34, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x600)) return 1;
+
+	// 0x3E: 4 byte addr, quad/quad
+	printf("Testing SPI flash command 0x3E...\n");
+	write_spiflash(test_data, test_len, 0x700, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x700)) return 1;
+
+	return 0;
+}
--- a/toolchains/libgloss
+++ b/toolchains/libgloss
--- a/tools/barstools
+++ b/tools/barstools
--- a/tools/chisel3
+++ b/tools/chisel3
--- a/tools/dromajo/dromajo-src
+++ b/tools/dromajo/dromajo-src
--- a/tools/dromajo/dromajo.mk
+++ b/tools/dromajo/dromajo.mk
@@ -0,0 +1,59 @@
+##############################################################
+# extra variables/targets ingested by the chipyard make system
+##############################################################
+
+DROMAJO_DIR = $(base_dir)/tools/dromajo/dromajo-src/src
+DROMAJO_LIB_NAME = dromajo_cosim
+DROMAJO_LIB = $(DROMAJO_DIR)/lib$(DROMAJO_LIB_NAME).a
+
+# Dromajo assumes using the default bootrom
+DROMAJO_ROM = $(base_dir)/bootrom/bootrom.rv64.img
+
+DTS_FILE = $(build_dir)/$(long_name).dts
+DROMAJO_DTB = $(build_dir)/$(long_name).dtb
+
+$(DTS_FILE): $(FIRRTL_FILE)
+
+$(DROMAJO_DTB): $(DTS_FILE)
+	dtc -I dts -O dtb -o $(DROMAJO_DTB) $(DTS_FILE)
+
+DROMAJO_SRCS = $(call lookup_srcs,$(DROMAJO_DIR),cc) $(call lookup_srcs,$(DROMAJO_DIR),h)
+
+$(DROMAJO_LIB): $(DROMAJO_SRCS)
+	$(MAKE) -C $(DROMAJO_DIR)
+
+# depending on where the simulation is done, use the auto-variable or the hardcoded defined one
+ifeq ($(BINARY),)
+DROMAJO_BIN = $(<)
+else
+DROMAJO_BIN = $(BINARY)
+endif
+
+DROMAJO_FLAGS = +drj_dtb=$(DROMAJO_DTB) +drj_rom=$(DROMAJO_ROM) +drj_bin=$(DROMAJO_BIN)
+
+DROMAJO_PARAMS_FILE    = $(build_dir)/$(long_name).dromajo_params.h
+DROMAJO_PARAMS_SYMLINK = $(build_dir)/dromajo_params.h
+
+$(DROMAJO_PARAMS_FILE): $(FIRRTL_FILE)
+
+$(DROMAJO_PARAMS_SYMLINK): $(DROMAJO_PARAMS_FILE)
+	rm -rf $(DROMAJO_PARAMS_SYMLINK)
+	ln -s $(DROMAJO_PARAMS_FILE) $(DROMAJO_PARAMS_SYMLINK)
+
+##################################################################
+# THE FOLLOWING MUST BE += operators
+##################################################################
+
+# simargs needed (i.e. like +drj_test=hello)
+ifdef ENABLE_DROMAJO
+EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS)
+
+# CC flags needed for all simulations
+EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR)
+
+# sourced needed for simulation
+EXTRA_SIM_SOURCES += $(DROMAJO_LIB)
+
+# requirements needed for simulation
+EXTRA_SIM_REQS += $(DROMAJO_PARAMS_SYMLINK) $(DROMAJO_LIB) $(DROMAJO_DTB)
+endif
--- a/tools/firrtl
+++ b/tools/firrtl
--- a/tools/treadle
+++ b/tools/treadle
--- a/Show More
+++ b/Show More