Merge pull request #1344 from ucb-bar/nocores

Add a config with no cores

.github/scripts/defaults.sh

@@ -26,7 +26,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif chipyard-nocores"
 grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -55,6 +55,7 @@ mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
 mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
+mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
 mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"

generators/chipyard/src/main/scala/Subsystem.scala

@@ -54,6 +54,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     case b: BoomTile => b.module.core.coreMonitorBundle
   }.toList
 
+  // No-tile configs have to be handled specially.
+  if (tiles.size == 0) {
+    // no PLIC, so sink interrupts to nowhere
+    require(!p(PLICKey).isDefined)
+    val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head)
+    val intSink = IntSinkNode(IntSinkPortSimple())
+    intSink := intNexus :=* ibus.toPLIC
+
+    // Need to have at least 1 driver to the tile notification sinks
+    tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
+    tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())
+    tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple())
+
+    // Sink reset vectors to nowhere
+    val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W)))
+    resetVectorSink := tileResetVectorNode
+  }
 
   // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
   // bus-couplings that are not asynchronous strips the bus name from the sink

generators/chipyard/src/main/scala/clocking/TileResetSetter.scala

@@ -33,9 +33,10 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
         Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0)))
       }
     })
-    tlNode.regmap((0 until nTiles).map({ i =>
-      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
-    }): _*)
+    if (nTiles > 0)
+      tlNode.regmap((0 until nTiles).map({ i =>
+        i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
+      }): _*)
 
     val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>
         n -> (tile_async_resets(i), r_tile_resets(i).io.q)

generators/chipyard/src/main/scala/config/NoCoreConfigs.scala

@@ -0,0 +1,9 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+
+// A empty config with no cores. Useful for testing
+class NoCoresConfig extends Config(
+  new chipyard.config.WithNoDebug ++
+  new chipyard.config.WithNoPLIC ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.util.{log2Up}
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.devices.tilelink.{BootROMLocated}
+import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
 import freechips.rocketchip.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
@@ -77,5 +77,9 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
 })
 
 class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
-    case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
+  case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
+})
+
+class WithNoPLIC extends Config((site, here, up) => {
+  case PLICKey => None
 })