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Merge branch 'main' into uart-patch

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-T.K.-
2024-01-02 11:13:23 -08:00
committed by GitHub
parent 482d9e9ff8 493e24ffa7
commit f8428b7eca
47 changed files with 239 additions and 129 deletions
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2
docs/Customization/Memory-Hierarchy.rst
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@@ -94,7 +94,7 @@ memory channel.
Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
and remove the off-chip link. This is done by adding a fragment like
``testchipip.WithScratchpad`` to your configuration and removing the
``testchipip.soc.WithScratchpad`` to your configuration and removing the
memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

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fpga/bootrom.rv32.img Executable file
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fpga/bootrom.rv64.img Executable file
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21
fpga/src/main/resources/vcu118/sdboot/sd.c
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@@ -22,7 +22,16 @@
#error Must define TL_CLK
#endif
#define F_CLK TL_CLK
#define F_CLK (TL_CLK)
// SPI SCLK frequency, in kHz
// We are using the 25MHz High Speed mode. If this speed is not supported by the
// SD card, consider changing to the Default Speed mode (12.5 MHz).
#define SPI_CLK 25000
// SPI clock divisor value
// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi
#define SPI_DIV (((F_CLK * 1000) / SPI_CLK) / 2 - 1)
static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
@@ -79,7 +88,9 @@ static inline void sd_cmd_end(void)
static void sd_poweron(void)
{
long i;
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
// HACK: frequency change
REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
for (i = 10; i > 0; i--) {
sd_dummy();
@@ -171,12 +182,10 @@ static int copy(void)
dputs("CMD18");
kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B);
kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B);
kprintf("LOADING ");
// TODO: Speed up SPI freq. (breaks between these two values)
//REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
sd_cmd_end();
return 1;

5
fpga/src/main/scala/arty/Configs.scala
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@@ -11,7 +11,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -30,7 +30,8 @@ class WithArtyTweaks extends Config(
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new testchipip.WithNoSerialTL
new testchipip.serdes.WithNoSerialTL ++
new testchipip.soc.WithNoScratchpads
)
class TinyRocketArtyConfig extends Config(

12
fpga/src/main/scala/arty100t/Configs.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import sifive.fpgashells.shell.{DesignKey}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -21,11 +21,15 @@ class WithNoDesignKey extends Config((site, here, up) => {
case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
})
// By default, this uses the on-board USB-UART for the TSI-over-UART link
// The PMODUART HarnessBinder maps the actual UART device to JD pin
class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new WithArty100TPMODUART ++
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
new WithArty100TJTAG ++
new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
@@ -36,8 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
new freechips.rocketchip.subsystem.WithoutTLMonitors)
@@ -56,5 +58,5 @@ class NoCoresArty100TConfig extends Config(
class BringupArty100TConfig extends Config(
new WithArty100TSerialTLToGPIO ++
new WithArty100TTweaks(freqMHz = 50) ++
new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new chipyard.ChipBringupHostConfig)

3
fpga/src/main/scala/arty100t/Harness.scala
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@@ -33,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
harnessSysPLLNode := clockOverlay.overlayOutput.node
val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",

58
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -20,12 +20,20 @@ import chipyard._
import chipyard.harness._
import chipyard.iobinders._
import testchipip._
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
ath.io_uart_bb.bundle <> port.io.uart
val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
harnessIO <> port.io.uart
val packagePinsWithPackageIOs = Seq(
("A9" , IOPin(harnessIO.rxd)),
("D10", IOPin(harnessIO.txd)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addIOB(io)
} }
ath.other_leds(1) := port.io.dropped
ath.other_leds(9) := port.io.tsi2tl_state(0)
ath.other_leds(10) := port.io.tsi2tl_state(1)
@@ -34,6 +42,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
}
})
class WithArty100TDDRTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: TLMemPort) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
@@ -83,3 +92,46 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
artyTh.xdc.clockDedicatedRouteFalse(clkIO)
}
})
// Maps the UART device to the on-board USB-UART
class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
harnessIO <> port.io
val packagePinsWithPackageIOs = Seq(
(rxdPin, IOPin(harnessIO.rxd)),
(txdPin, IOPin(harnessIO.txd)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addIOB(io)
} }
}
})
// Maps the UART device to PMOD JD pins 3/7
class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
class WithArty100TJTAG extends HarnessBinder({
case (th: HasHarnessInstantiators, port: JTAGPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
harnessIO <> port.io
ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
ath.sdc.addGroup(clocks = Seq("JTCK"))
ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
val packagePinsWithPackageIOs = Seq(
("F4", IOPin(harnessIO.TCK)),
("D2", IOPin(harnessIO.TMS)),
("E2", IOPin(harnessIO.TDI)),
("D4", IOPin(harnessIO.TDO))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addPullup(io)
} }
}
})

6
fpga/src/main/scala/nexysvideo/Configs.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import sifive.fpgashells.shell.{DesignKey}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config(
new WithNexysVideoUARTTSI ++
new WithNexysVideoDDRTL ++
new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
@@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config(
new WithNexysVideoUARTTSI ++
new WithNoDesignKey ++
new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++

2
fpga/src/main/scala/nexysvideo/HarnessBinders.scala
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@@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams}
import chipyard._
import chipyard.harness._
import testchipip._
import chipyard.iobinders._
class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({

2
fpga/src/main/scala/vc707/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness._

2
fpga/src/main/scala/vcu118/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard._
import chipyard.harness._

2
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import chipyard.{BuildSystem}

2
fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
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@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
import testchipip.{TSIHostWidgetIO}
import testchipip.tsi.{TSIHostWidgetIO}
import chipyard.fpga.vcu118.{FMCPMap}

2
fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
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@@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule}
class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
with sifive.blocks.devices.i2c.HasPeripheryI2C
with testchipip.HasPeripheryTSIHostWidget
with testchipip.tsi.HasPeripheryTSIHostWidget
{
override lazy val module = new BringupVCU118DigitalTopModule(this)
}

2
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
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@@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.harness._
import chipyard.iobinders._

2
fpga/src/main/scala/vcu118/bringup/IOBinders.scala
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@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}

3
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
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@@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
import testchipip.util.{TLSinkSetter}
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}

2
generators/caliptra-aes-acc

Submodule generators/caliptra-aes-acc updated: 15d2f85262...82fa7080f4

16
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -13,13 +13,13 @@ import freechips.rocketchip.devices.tilelink._
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
@@ -40,7 +40,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with testchipip.CanHaveTraceIOModuleImp
with testchipip.cosim.CanHaveTraceIOModuleImp
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp

2
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr

3
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -14,7 +14,8 @@ import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci._
import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer}
import testchipip.boot.{TLTileResetCtrl}
import testchipip.clocking.{ClockGroupFakeResetSynchronizer}
case class ChipyardPRCIControlParams(
slaveWhere: TLBusWrapperLocation = CBUS,

4
generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
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@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
import testchipip._
import testchipip.clocking._
// This module adds a TileLink memory-mapped clock divider to the clock graph
// The output clock/reset pairs from this module should be synchronized later
@@ -38,7 +38,7 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
val reg = Module(new AsyncResetRegVec(w=divBits, init=0))
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
val divider = Module(new ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
divider.io.clockIn := sources(i).clock
// busReset is expected to be high for a long time, since reset will take a while to propagate
// to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock

4
generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
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@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
import testchipip._
import testchipip.clocking._
case class ClockSelNode()(implicit valName: ValName)
extends MixedNexusNode(ClockImp, ClockGroupImp)(
@@ -40,7 +40,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
sel := reg.io.q
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux")
val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
mux.io.sel := sel
mux.io.resetAsync := asyncReset.asAsyncReset
sinks(i).clock := mux.io.clockOut

16
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -61,12 +61,16 @@ class AbstractConfig extends Config(
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( // add a serial-tilelink interface
client = Some(testchipip.SerialTLClientParams(idBits = 4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
width = 32 // serial-tilelink interface with 32 lanes
))) ++
new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
width = 32 // serial-tilelink interface with 32 lanes
)
)) ++
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad
size = 64 * 1024) ++
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART

24
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -3,7 +3,7 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{MBUS, SBUS}
import testchipip.{OBUS}
import testchipip.soc.{OBUS}
// A simple config demonstrating how to set up a basic chip in Chipyard
class ChipLikeRocketConfig extends Config(
@@ -22,16 +22,16 @@ class ChipLikeRocketConfig extends Config(
//==================================
// Set up I/O
//==================================
new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO
new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory
new testchipip.serdes.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO
new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//==================================
// Set up buses
//==================================
new testchipip.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
new testchipip.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory
new testchipip.soc.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
new testchipip.soc.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory
//==================================
// Set up clock./reset
@@ -60,17 +60,17 @@ class ChipBringupHostConfig extends Config(
//=============================
// Setup the SerialTL side on the bringup device
//=============================
new testchipip.WithSerialTLWidth(4) ++ // match width with the chip
new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host
idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000
new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
new testchipip.serdes.WithSerialTLWidth(4) ++ // match width with the chip
new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host
idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000
new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
//============================
// Setup bus topology on the bringup system
//============================
new testchipip.WithOffchipBusClient(SBUS, // offchip bus hangs off the SBUS
new testchipip.soc.WithOffchipBusClient(SBUS, // offchip bus hangs off the SBUS
blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly
new testchipip.WithOffchipBus ++ // offchip bus
new testchipip.soc.WithOffchipBus ++ // offchip bus
//=============================
// Set up memory on the bringup system
@@ -80,7 +80,7 @@ class ChipBringupHostConfig extends Config(
//=============================
// Generate the TSI-over-UART side of the bringup system
//=============================
new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++ // nonstandard baud rate to improve performance
new testchipip.tsi.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++ // nonstandard baud rate to improve performance
//=============================
// Set up clocks of the bringup system

4
generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
View File

@@ -19,14 +19,14 @@ class GB1MemoryRocketConfig extends Config(
// DOC include start: mbusscratchpadrocket
class MbusScratchpadOnlyRocketConfig extends Config(
new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: mbusscratchpadrocket
class SbusScratchpadRocketConfig extends Config(
new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

4
generators/chipyard/src/main/scala/config/NoCConfigs.scala
View File

@@ -146,7 +146,7 @@ class MultiNoCConfig extends Config(
* L2 3 | MI | Cache[3] | 6
* DRAM 0 | MO | system[0] | 3
* DRAM 1 | MO | system[1] | 5
* extram | MO | serial_tl_0 | 9
* spad | MO | ram[0] | 9
*/
// DOC include start: SharedNoCConfig
class SharedNoCConfig extends Config(
@@ -169,7 +169,7 @@ class SharedNoCConfig extends Config(
"Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 5,
"serial_tl_0" -> 9))
"ram[0]" -> 9))
)) ++
new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(

5
generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
View File

@@ -4,8 +4,9 @@ import org.chipsalliance.cde.config.{Config}
// A empty config with no cores. Useful for testing
class NoCoresConfig extends Config(
new testchipip.WithNoBootAddrReg ++
new testchipip.WithNoCustomBootPin ++
new testchipip.soc.WithNoScratchpads ++
new testchipip.boot.WithNoBootAddrReg ++
new testchipip.boot.WithNoCustomBootPin ++
new chipyard.config.WithNoCLINT ++
new chipyard.config.WithNoBootROM ++
new chipyard.config.WithBroadcastManager ++

22
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -22,13 +22,13 @@ class SmallSPIFlashRocketConfig extends Config(
class SimBlockDeviceRocketConfig extends Config(
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class BlockDeviceModelRocketConfig extends Config(
new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel
new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
new testchipip.iceblk.WithBlockDevice ++ // add block-device module to periphery bus
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -53,10 +53,10 @@ class MMIORocketConfig extends Config(
class LBWIFRocketConfig extends Config(
new chipyard.config.WithOffchipBusFrequency(500) ++
new testchipip.WithOffchipBusClient(MBUS) ++
new testchipip.WithOffchipBus ++
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new testchipip.soc.WithOffchipBusClient(MBUS) ++
new testchipip.soc.WithOffchipBus ++
new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -69,10 +69,10 @@ class dmiRocketConfig extends Config(
// DOC include end: DmiRocket
class ManyPeripheralsRocketConfig extends Config(
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
new testchipip.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS
new testchipip.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus
new testchipip.soc.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS
new testchipip.soc.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory
new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
@@ -84,7 +84,7 @@ class ManyPeripheralsRocketConfig extends Config(
class UARTTSIRocketConfig extends Config(
new chipyard.harness.WithSerialTLTiedOff ++
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.config.WithMemoryBusFrequency(10) ++
new chipyard.config.WithFrontBusFrequency(10) ++
new chipyard.config.WithPeripheryBusFrequency(10) ++

4
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -12,7 +12,8 @@ class RocketConfig extends Config(
new chipyard.config.AbstractConfig)
class TinyRocketConfig extends Config(
new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports
new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports
new testchipip.soc.WithNoScratchpads ++ // All memory is the Rocket TCMs
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
@@ -36,6 +37,7 @@ class RV32RocketConfig extends Config(
// DOC include start: l1scratchpadrocket
class ScratchpadOnlyRocketConfig extends Config(
new chipyard.config.WithL2TLBs(0) ++
new testchipip.soc.WithNoScratchpads ++ // remove subsystem scratchpads, confusingly named, does not remove the L1D$ scratchpads
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem

18
generators/chipyard/src/main/scala/config/SodorConfigs.scala
View File

@@ -7,7 +7,8 @@ import org.chipsalliance.cde.config.{Config}
class Sodor1StageConfig extends Config(
// Create a Sodor 1-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.soc.WithNoScratchpads ++ // No scratchpads
new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -16,7 +17,8 @@ class Sodor1StageConfig extends Config(
class Sodor2StageConfig extends Config(
// Create a Sodor 2-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.soc.WithNoScratchpads ++ // No scratchpads
new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -25,7 +27,8 @@ class Sodor2StageConfig extends Config(
class Sodor3StageConfig extends Config(
// Create a Sodor 1-stage core with two ports
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.soc.WithNoScratchpads ++ // No scratchpads
new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -34,7 +37,8 @@ class Sodor3StageConfig extends Config(
class Sodor3StageSinglePortConfig extends Config(
// Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.soc.WithNoScratchpads ++ // No scratchpads
new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -43,7 +47,8 @@ class Sodor3StageSinglePortConfig extends Config(
class Sodor5StageConfig extends Config(
// Create a Sodor 5-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.soc.WithNoScratchpads ++ // No scratchpads
new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -52,7 +57,8 @@ class Sodor5StageConfig extends Config(
class SodorUCodeConfig extends Config(
// Construct a Sodor microcode-based single-bus core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.soc.WithNoScratchpads ++ // No scratchpads
new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++

2
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
View File

@@ -45,7 +45,7 @@ class SpikeUltraFastDevicesConfig extends Config(
new chipyard.harness.WithSimBlockDevice ++
new chipyard.harness.WithLoopbackNIC ++
new icenet.WithIceNIC ++
new testchipip.WithBlockDevice ++
new testchipip.iceblk.WithBlockDevice ++
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++

2
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -43,6 +43,6 @@ class NonBlockingTraceGenL2Config extends Config(
class NonBlockingTraceGenL2RingConfig extends Config(
new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new testchipip.WithRingSystemBus ++
new testchipip.soc.WithRingSystemBus ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new AbstractTraceGenConfig)

4
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
View File

@@ -13,9 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
import chipyard._
import chipyard.clocking._
import testchipip.{OffchipBusKey}
import testchipip.{OffchipBusKey}
import testchipip.soc.{OffchipBusKey}
// The default RocketChip BaseSubsystem drives its diplomatic clock graph
// with the implicit clocks of Subsystem. Don't do that, instead we extend

2
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -11,7 +11,7 @@ import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams}
import sodor.common.{SodorTileAttachParams}
import ibex.{IbexTileAttachParams}
import testchipip._
import testchipip.cosim.{TracePortKey, TracePortParams}
import barf.{TilePrefetchingMasterPortParams}
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {

2
generators/chipyard/src/main/scala/example/FlatChipTop.scala
View File

@@ -14,7 +14,7 @@ import chipyard.harness.{BuildTop}
import chipyard.clocking._
import chipyard.iobinders._
import barstools.iocell.chisel._
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
class WithFlatChipTop extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => new FlatChipTop()(p)

5
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
View File

@@ -11,7 +11,10 @@ import freechips.rocketchip.util.{PlusArg}
import freechips.rocketchip.subsystem.{CacheBlockBytes}
import freechips.rocketchip.devices.debug.{SimJTAG}
import freechips.rocketchip.jtag.{JTAGIO}
import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI}
import testchipip.serdes.{SerialTLKey}
import testchipip.uart.{UARTAdapter}
import testchipip.dram.{SimDRAM}
import testchipip.tsi.{TSIHarness, SimTSI}
import chipyard.harness.{BuildTop}
// A "flat" TestHarness that doesn't use IOBinders

9
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -12,7 +12,14 @@ import freechips.rocketchip.util._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.devices.debug.{SimJTAG}
import barstools.iocell.chisel._
import testchipip._
import testchipip.dram.{SimDRAM}
import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
import testchipip.soc.{TestchipSimDTM}
import testchipip.spi.{SimSPIFlashModel}
import testchipip.uart.{UARTAdapter, UARTToSerial}
import testchipip.serdes.{SerialWidthAdapter}
import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel}
import testchipip.cosim.{SpikeCosim}
import icenet.{NicLoopback, SimNetwork}
import chipyard._
import chipyard.clocking.{HasChipyardPRCI}

13
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View File

@@ -23,7 +23,13 @@ import tracegen.{TraceGenSystemModuleImp}
import barstools.iocell.chisel._
import testchipip._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}
import testchipip.boot.{CanHavePeripheryCustomBootPin}
import testchipip.util.{ClockedIO}
import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
import testchipip.cosim.{CanHaveTraceIOModuleImp, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
@@ -110,7 +116,10 @@ object GetSystemParameters {
}
class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString)))
case IOBinders => {
val upMap = up(IOBinders)
upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
}
})
class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](

8
generators/chipyard/src/main/scala/iobinders/Ports.scala
View File

@@ -4,9 +4,13 @@ import chisel3._
import chisel3.experimental.{Analog}
import sifive.blocks.devices.uart.{UARTPortIO}
import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO}
import sifive.blocks.devices.i2c.{I2CPort}
import sifive.blocks.devices.gpio.{GPIOPortIO}
import testchipip._
import testchipip.util.{ClockedIO}
import testchipip.serdes.{TLSerdesser, SerialIO, SerialTLParams}
import testchipip.spi.{SPIChipIO}
import testchipip.cosim.{TraceOutputTop, SpikeCosimConfig}
import testchipip.iceblk.{BlockDeviceIO, BlockDeviceConfig}
import testchipip.tsi.{UARTTSIIO}
import icenet.{NICIOvonly, NICConfig}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}

2
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import sifive.blocks.devices.uart._
import testchipip._
import testchipip.tsi.{SerialRAM}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import junctions.{NastiKey, NastiParameters}

21
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -13,7 +13,8 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams}
import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
import testchipip.cosim.{TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import scala.math.{min, max}
@@ -101,7 +102,7 @@ class WithFireSimDesignTweaks extends Config(
// Required: Bake in the default FASED memory model
new WithDefaultMemModel ++
// Optional: reduce the width of the Serial TL interface
new testchipip.WithSerialTLWidth(4) ++
new testchipip.serdes.WithSerialTLWidth(4) ++
// Required*: Scale default baud rate with periphery bus frequency
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
// Optional: Adds IO to attach tracerV bridges
@@ -109,7 +110,7 @@ class WithFireSimDesignTweaks extends Config(
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
// Optional: Removing this will require using an initramfs under linux
new testchipip.WithBlockDevice
new testchipip.iceblk.WithBlockDevice
)
// Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
@@ -154,7 +155,7 @@ class WithFireSimConfigTweaks extends Config(
class WithMinimalFireSimHighPerfConfigTweaks extends Config(
new WithFireSimHighPerfClocking ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new testchipip.WithMbusScratchpad ++
new testchipip.soc.WithMbusScratchpad ++
new WithMinimalFireSimDesignTweaks
)
@@ -164,8 +165,8 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
new WithFireSimHighPerfClocking ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
new testchipip.WithBlockDevice(true) ++ // add in block device
new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device
new WithMinimalFireSimDesignTweaks
)
@@ -260,11 +261,11 @@ class FireSimSmallSystemConfig extends Config(
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
client = Some(testchipip.SerialTLClientParams(idBits = 4)),
new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
width = 32
))) ++
new testchipip.WithBlockDevice ++
new testchipip.iceblk.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
new chipyard.RocketConfig)
@@ -342,7 +343,7 @@ class FireSim16LargeBoomConfig extends Config(
class FireSimNoMemPortConfig extends Config(
new WithDefaultFireSimBridges ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new testchipip.WithMbusScratchpad ++
new testchipip.soc.WithMbusScratchpad ++
new WithFireSimConfigTweaks ++
new chipyard.RocketConfig)

2
generators/testchipip

Submodule generators/testchipip updated: 50a05b0782...c13b8f658b

38
scripts/build-setup.sh
View File

@@ -29,7 +29,8 @@ usage() {
echo " 7. FireSim pre-compile sources"
echo " 8. FireMarshal"
echo " 9. FireMarshal pre-compile default buildroot Linux sources"
echo " 10. Runs repository clean-up"
echo " 10. Install CIRCT"
echo " 11. Runs repository clean-up"
echo ""
echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**"
echo ""
@@ -152,16 +153,6 @@ if run_step "1"; then
conda activate $CYDIR/.conda-env
exit_if_last_command_failed
# install circt into conda
git submodule update --init $CYDIR/tools/install-circt &&
$CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-f circt-full-shared-linux-x64.tar.gz \
-i $CONDA_PREFIX \
-v version-file \
-x $CYDIR/conda-reqs/circt.json \
-g null
exit_if_last_command_failed
# Conda Setup
# Provide a sourceable snippet that can be used in subshells that may not have
# inhereted conda functions that would be brought in under a login shell that
@@ -273,8 +264,31 @@ if run_step "8"; then
popd
fi
# do misc. cleanup for a "clean" git status
if run_step "10"; then
# install circt into conda
if run_step "1"; then
PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE
else
if [ -z "$RISCV" ] ; then
error "ERROR: If conda initialization skipped, \$RISCV variable must be defined."
exit 1
fi
PREFIX=$RISCV
fi
git submodule update --init $CYDIR/tools/install-circt &&
$CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-f circt-full-shared-linux-x64.tar.gz \
-i $PREFIX \
-v version-file \
-x $CYDIR/conda-reqs/circt.json \
-g null
exit_if_last_command_failed
fi
# do misc. cleanup for a "clean" git status
if run_step "11"; then
begin_step "10" "Cleaning up repository"
$CYDIR/scripts/repo-clean.sh
exit_if_last_command_failed

2
sims/firesim

Submodule sims/firesim updated: 73fe6a51b2...e975893595

2
variables.mk
View File

@@ -97,7 +97,7 @@ ifeq ($(SUB_PROJECT),testchipip)
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= chipyard.unittest
CONFIG ?= TestChipUnitTestConfig
CONFIG_PACKAGE ?= testchipip
CONFIG_PACKAGE ?= testchipip.test
GENERATOR_PACKAGE ?= chipyard
TB ?= TestDriver
TOP ?= UnitTestSuite