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Cleanup VCS's csrc directory | Fix small doc typo

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abejgonzalez
2020-08-21 16:14:07 -07:00
parent 2168813da0
commit fa97359516
2 changed files with 14 additions and 6 deletions
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2
docs/Simulation/Software-RTL-Simulation.rst
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@@ -195,5 +195,5 @@ When building the verilator simulator there are some additional options:
The ``VERILATOR_THREADS=<num>`` option enables the compiled Verilator simulator to use ``<num>`` parallel threads.
On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``NUMACTL=1`` to enable ``numactl``.
By enabling this, you will use CHipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator-<name> <simulator-args>``.
By enabling this, you will use Chipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator-<name> <simulator-args>``.
Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation).

18
sims/vcs/Makefile
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@@ -43,14 +43,22 @@ VCS = vcs -full64
VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
#########################################################################################
# vcs build paths
#########################################################################################
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
#########################################################################################
# vcs simulator rules
#########################################################################################
$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@
rm -rf $(model_dir)
$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir)
$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \
rm -rf $(model_dir_debug)
$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug) \
+define+DEBUG
#########################################################################################
@@ -65,10 +73,10 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
clean-sim:
rm -rf csrc/ $(sim) ucli.key vc_hdrs.h
rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key
clean-sim-debug:
rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h
rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key