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make sure verilator builds correctly

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Howard Mao
2017-07-20 19:44:23 +00:00
parent 6175249845
commit fae57b6daa
1 changed files with 1 additions and 1 deletions
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verisim/Makefile
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@@ -14,7 +14,7 @@ default: $(sim)
debug: $(sim_debug)
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
include $(base_dir)/Makefrag