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corner case

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joey0320
2023-05-04 21:51:00 -07:00
parent 60e80a772e
commit fec43fc147
1 changed files with 1 additions and 1 deletions
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scripts/uniquify-module-names.py
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@@ -53,7 +53,7 @@ def get_modules_in_verilog_file(file):
for line in lines: for line in lines:
words = line.split() words = line.split()
if len(words) > 0 and words[0] == "module": if len(words) > 0 and words[0] == "module":
module_names.append(words[1].replace("(", "")) module_names.append(words[1].replace("(", "").replace(")", "").replace(";", ""))
return module_names return module_names
def get_modules_in_filelist(verilog_module_filename, cc_filelist): def get_modules_in_filelist(verilog_module_filename, cc_filelist):