power flow makefiles

vlsi/example-tools.yml

@@ -2,10 +2,10 @@
 vlsi.core.build_system: make
 # Genus options
 vlsi.core.synthesis_tool: "hammer.synthesis.genus"
-synthesis.genus.version: "211"
+synthesis.genus.version: "221"
 # Innovus options
 vlsi.core.par_tool: "hammer.par.innovus"
-par.innovus.version: "211"
+par.innovus.version: "221"
 par.innovus.design_flow_effort: "standard"
 par.inputs.gds_merge: true
 # Calibre options
@@ -17,7 +17,7 @@ lvs.calibre.version: "2022.2_24.16"
 vlsi.core.sim_tool: "hammer.sim.vcs"
 sim.vcs.version: "S-2021.09-SP1-1"
 # Voltus options
-vlsi.core.power_tool: "hammer.power.voltus"
-power.joules.version: "211"
-power.voltus.version: "211_ISR3"
+vlsi.core.power_tool: "hammer.power.joules"
+power.joules.version: "221"
+power.voltus.version: "221_ISR3"
 # NOTE (about VCS+Voltus versions): if using FSDB, the VCS version should be approx 2 years older than the Voltus version for compatibility

vlsi/power.mk

@@ -3,9 +3,12 @@ POWER_RTL_CONF = $(OBJ_DIR)/power-rtl-inputs.yml
 POWER_SYN_CONF = $(OBJ_DIR)/power-syn-inputs.yml
 POWER_PAR_CONF = $(OBJ_DIR)/power-par-inputs.yml
 POWER_PAR_HIER_CONF = $(OBJ_DIR)/power-par-$(VLSI_TOP)-inputs.yml
+REUSE_DB = no
 
 .PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF) $(POWER_PAR_HIER_CONF)
 
+include radiance.mk
+
 $(POWER_CONF): $(VLSI_RTL) check-binary
 	mkdir -p $(dir $@)
 	echo "power.inputs:" > $@
@@ -21,19 +24,30 @@ else
 endif
 	echo "  ]" >> $@
 endif
+ifneq ($(START_TIME), )
+	echo "  start_times: ['$(START_TIME)']" >> $@
+else
 	echo "  start_times: ['0ns']" >> $@
+endif
+ifneq ($(END_TIME), )
+	echo "  end_times: [" >> $@
+	echo "    '$(END_TIME)'" >> $@
+	echo "  ]" >> $@
+else
 	echo "  end_times: [" >> $@
 	echo "    '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
 	echo "  ]" >> $@
+endif
 
 $(POWER_RTL_CONF): $(VLSI_RTL)
 	echo "vlsi.core.power_tool: hammer.power.joules" > $@
 	echo "power.inputs:" >> $@
 	echo "  level: rtl" >> $@
+	echo "  reuse_db: $(REUSE_DB)" >> $@
 	echo "  input_files:" >> $@
-	for x in $$(cat $(VLSI_RTL)); do \
+	for x in $$(cat $(build_dir)/syn.f); do \
 		echo '    - "'$$x'"' >> $@; \
-	done
+	done # for x in $$(cat $(VLSI_RTL)); do \
 
 $(POWER_SYN_CONF): $(VLSI_RTL)
 	echo "vlsi.core.power_tool: hammer.power.joules" > $@

vlsi/radiance.mk

@@ -0,0 +1,6 @@
+TIMEOUT_CYCLES = 0
+timeout_cycles = 0
+START_TIME = 49000ns
+override SIM_FLAGS += +loadmem=$(BINARY) +vcs+initreg+random
+override VCS_NONCC_OPTS += +vcs+initreg+random
+override EXTRA_SIM_PREPROC_DEFINES += +define+DPI_DISABLE +define+NDEBUG +define+VLSI_SIM +define+SYNTHESIS

vlsi/sim.mk

@@ -4,13 +4,16 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
 
 .PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF)
 
+include radiance.mk
+
 $(SIM_CONF): $(sim_common_files) check-binary
 	mkdir -p $(dir $@)
 	echo "sim.inputs:" > $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  tb_name: ''" >> $@  # don't specify -top
 	echo "  input_files:" >> $@
-	for x in $$(cat $(MODEL_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
+	# plusarg_reader is bugged, TODO perhaps raise the issue again in chipyard #1388 and #1442
+	for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(GEN_COLLATERAL_DIR)/GenericDeserializer.sv $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@