abejgonzalez
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b0fc0457aa
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Use Chipyard configs as base (Arty)
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2020-11-05 20:46:03 -08:00 |
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abejgonzalez
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9a5b67bf8c
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Use Chipyard configs as a base (VCU118)
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2020-11-05 20:30:49 -08:00 |
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abejgonzalez
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083f34ab23
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Revert Chipyard system | Create new VCU118 Chipyard system
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2020-11-05 15:44:54 -08:00 |
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abejgonzalez
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a7ab0dab59
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Updated VCU118 | Bumped naming on Arty
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2020-11-05 13:59:10 -08:00 |
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abejgonzalez
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3994bcecdf
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Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
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2020-11-05 11:08:36 -08:00 |
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abejgonzalez
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c619df2c00
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Merge branch 'local-fpga-temp' into local-fpga-support
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2020-11-05 11:01:56 -08:00 |
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David Biancolin
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f504b7a0f5
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[clocking] Improve reference clock selection using a multiple-of-fastest strategy
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2020-11-03 09:14:55 -08:00 |
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David Biancolin
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aa4a44925e
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[clocking] Add ScalaTests for the divider-only PLL configurator
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2020-11-03 09:14:55 -08:00 |
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David Biancolin
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f387634a41
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[clocking] Bound SimplePllConfiguration by maximum reference freq
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2020-11-03 09:14:55 -08:00 |
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David Biancolin
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946a191221
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[clocking] Provide a default div for ClockDividerN sv implementation (#706)
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2020-11-03 12:14:18 -05:00 |
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Jerry Zhao
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2d010b63f3
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Merge branch 'dev' into lazy-iobinders
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2020-11-02 10:02:44 -08:00 |
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Jerry Zhao
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7b83da054a
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Clean up HarnessBinders
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2020-10-28 16:18:22 -07:00 |
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Jerry Zhao
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f4d70128c0
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Remove redundant ChipTop reset synchronizer
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2020-10-28 15:37:31 -07:00 |
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Abraham Gonzalez
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0eca51ba4d
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Reorganize into bringup/simple | Bump sifive-blocks
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2020-10-27 12:57:34 -07:00 |
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Abraham Gonzalez
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3c42e2cae7
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Fixed BootROM | Updated HarnessBinders
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2020-10-26 18:15:58 -07:00 |
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Jerry Zhao
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93e57ef230
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Make the ChipTop reset pin async always
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2020-10-26 15:18:34 -07:00 |
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Jerry Zhao
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d61b31a6fe
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Merge pull request #702 from ucb-bar/multirocc-gemmini
Add MultiRoCCGemmini config fragment
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2020-10-26 10:03:26 -07:00 |
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Fang, Zitao
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4fdb9eb6b0
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Merge pull request #647 from ucb-bar/verilator-makefile-fix
Fix Verilator Simulation run-binary-debug Error
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2020-10-23 21:54:58 -07:00 |
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Zitao Fang
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abbeb2af9e
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Fixed comments
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2020-10-23 17:00:56 -07:00 |
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Zitao Fang
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0c4dcffb0d
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Fixed lowercase p bug
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2020-10-23 16:39:56 -07:00 |
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Jerry Zhao
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ac19117ec5
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Add MultiRoCCGemmini config fragment
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2020-10-23 15:41:49 -07:00 |
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Abraham Gonzalez
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a07369acaf
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Merge remote-tracking branch 'ch/lazy-iobinders' into local-fpga-temp
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2020-10-20 21:23:11 -07:00 |
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Jerry Zhao
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7a55c55aa3
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Fix no-MBUS configs
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2020-10-20 01:12:28 -07:00 |
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Jerry Zhao
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e0bf907a06
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Merge remote-tracking branch 'origin/dev' into lazy-iobinders
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2020-10-19 13:22:01 -07:00 |
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Abraham Gonzalez
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dd358f45ab
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UART Working... Bumped to newer fpga-shells
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2020-10-19 11:29:25 -07:00 |
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Jerry Zhao
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f3d666d2b7
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Clarify HarnessBinders ClassTag naming
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2020-10-19 10:16:44 -07:00 |
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Jerry Zhao
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9927231bc4
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Support lazy-iobinders
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2020-10-17 22:47:50 -07:00 |
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David Biancolin
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1b94e7f10c
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
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2020-10-16 23:21:20 +00:00 |
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Alon Amid
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6eaac63e1b
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address PR comments
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2020-10-16 06:34:26 +00:00 |
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Albert Magyar
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84e0bf7338
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Don't annotate cores with FAMEModelAnnotations
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2020-10-15 12:25:39 -07:00 |
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abejgonzalez
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9ba4918cb8
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Inject MMCDevice into TLSPI Node
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2020-10-15 11:46:42 -07:00 |
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David Biancolin
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74c1c9d7ab
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Punch out reset in AXI4MMIO IOBinder
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2020-10-15 11:28:36 -07:00 |
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Alon Amid
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2c935b4ad7
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pull firesim mem model config into firesim tweaks
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2020-10-15 17:07:51 +00:00 |
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Alon Amid
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4a317b0cab
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differentiate default config package delimiter
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2020-10-15 17:07:20 +00:00 |
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David Biancolin
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9c8d2948af
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[firechip] Fix a broken config
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2020-10-14 15:33:32 -07:00 |
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David Biancolin
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6aefb73ab5
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
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2020-10-14 15:29:00 -07:00 |
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abejgonzalez
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949d60597f
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Revert "Support evaluation of HarnessBinders in LazyModule context"
This reverts commit 9c298eedfe.
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2020-10-14 14:50:38 -07:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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David Biancolin
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211c33f996
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Address comments in #690
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2020-10-14 14:42:45 -07:00 |
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abejgonzalez
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341a6cc48d
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Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp
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2020-10-13 16:23:41 -07:00 |
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abejgonzalez
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5bbd865447
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Add MMC Device section to the DTS
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2020-10-13 16:18:00 -07:00 |
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Jerry Zhao
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9c298eedfe
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Support evaluation of HarnessBinders in LazyModule context
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2020-10-13 15:10:41 -07:00 |
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Jerry Zhao
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0c46ed1676
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Rename testchip_fesvr to testchip_tsi
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2020-10-09 09:34:20 -07:00 |
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Jerry Zhao
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25129c27ca
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Add testchip_fesvr to uncondtionally used resources
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2020-10-09 09:27:58 -07:00 |
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Jerry Zhao
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d71c3b6357
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Unify htif implementation with firesim
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2020-10-09 09:27:58 -07:00 |
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David Biancolin
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986b5831c8
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[clocking] Sketch out a topology that puts the MBUS is a separate domain
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2020-10-09 07:23:17 -07:00 |
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David Biancolin
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30b278687b
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[clocking] Also aggregate clocks in AsyncClockGroup
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2020-10-09 07:13:55 -07:00 |
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dunn
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252f9c6a12
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Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
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2020-10-07 11:55:16 -07:00 |
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David Biancolin
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392d5b0801
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[clocking] Synchronize all output clocks from DividerOnly generator
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2020-10-07 09:32:48 -07:00 |
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dunn
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a67318928a
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Bumping submodules to upstream dev's commits.
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2020-10-07 09:02:30 -07:00 |
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