Commit Graph

12 Commits

Author SHA1 Message Date
Albert Ou
361a9bf1d8 toolchains: Flatten esp-tools submodule 2019-10-02 13:16:01 -07:00
Colin Schmidt
1c3e203385 Ignore hammer log files (#200) 2019-08-15 08:46:37 -07:00
Abraham Gonzalez
ddfd47055a Merge pull request #182 from ucb-bar/emacs-tmp-ignore
Ignore emacs temp files
2019-07-30 15:00:52 -06:00
Jerry Zhao
91107ce043 Ignore emacs temp files 2019-07-29 15:33:31 -07:00
Jerry Zhao
0894919404 Ignore emacs temp files 2019-07-19 15:07:03 -07:00
Bastian Koppelmann
ed37f1d01b gitignore: add env.sh and riscv-tools-install
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-05-31 17:31:26 +02:00
Jerry Zhao
a4d4101cf4 Fix bootrom symlink, update .gitignore to only ignore bootrom directory 2019-05-11 13:26:31 -07:00
abejgonzalez
c364869563 default to .gitignoring all files in verisim/vsim | read verilator.mk 2019-03-12 14:39:15 -07:00
abejgonzalez
82273107c1 makefile changes/split | add scripts 2019-03-12 14:39:15 -07:00
Paul Rigge
ddf3159d61 Bump rocket, make possible to use published deps (#47)
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
2019-03-06 18:22:21 -08:00
Howard Mao
adb8c80ab3 change up gitignore rules 2017-02-07 17:37:26 -08:00
Howard Mao
7074420aba initial commit 2016-10-21 16:03:26 -07:00