Commit Graph

14 Commits

Author SHA1 Message Date
Jerry Zhao
abc75e9b95 Fix Reset bug 2020-08-07 17:50:23 -07:00
Jerry Zhao
9e443130b9 Merge remote-tracking branch 'origin/dev' into diplomatic-clocks 2020-08-05 14:21:16 -07:00
Jerry Zhao
578ae6fca2 Bump to July 2020 rocketchip 2020-08-04 14:00:02 -07:00
Jerry Zhao
b719919934 Add RANDOM_SEED variable to set random init for VCS and Verilator simulations 2020-07-20 18:25:18 -07:00
Jerry Zhao
a1cc62b85a Bump Rocket-chip again 2020-06-20 12:28:03 -07:00
Jerry Zhao
d245df9133 Bump Rocketchip to June 2020 for Tile changes 2020-06-18 17:25:31 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
Colin Schmidt
43f6083b69 Many changes to begin the compilation with RC-1.3
Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.

BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.

The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork

Treadle is bumped to its release branch
2020-05-05 15:14:24 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
Abraham Gonzalez
3d253c0f67 [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder
2020-03-30 17:04:45 -07:00
Jerry Zhao
ebfa545344 Generator unification 2020-02-13 12:33:28 -08:00
Jerry Zhao
05f17f5b99 [tracegen] Add tracegen support for the BOOM L1D (#362)
* [tracegen] Add tracegen support for the BOOM L1D

* [tracegen] Split up BOOM Tracegen mixin and shim.

* [ci] Fix tracegen hash for testing
2020-01-23 16:01:32 -08:00
Colin Schmidt
86a473dbf6 Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
2019-12-12 13:39:09 -08:00
Howard Mao
6a3212c6d7 add tracegen project 2019-08-30 11:38:07 -07:00