[WIP] Minimally elaborating design
Bring up a feature-complete Chipyard stage
Pull in Makefrag generation; Bump submodules
Update config generation, and global reset scheme
Bump submodules; clean up
Bump FireSim
Remove some unhygenic comments / WS
Remove the rocketchip subproject
[CI] Lengthen ariane tests timeout
Address some remaining reviewer comments
[firechip] Refresh a Field that cannot be used across repeated instantiations
Bump all submodules
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019
* Fix subprojects that aren't tested from normal sims
* Fix firechip for chisel 3.2.0 and rc bump
* Bump boom for bug fix rebase
* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]
* Bump boom for rc bump fix to bug fix
* Bump FireSim for CI check
* Bump FireSim
* Bump submodules after merge
