Fix tracegen target and add to CI

2019-10-13 05:44:57 -07:00
parent ced4d2eea0
commit 05af2f9a9c
12 changed files with 145 additions and 4 deletions
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -288,6 +288,35 @@ jobs:
                key: hwacha-{{ .Branch }}-{{ .Revision }}
                paths:
                    - "/home/riscvuser/project"
+    prepare-tracegen:
+        docker:
+            - image: riscvboom/riscvboom-images:0.0.12
+        environment:
+            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
+            TERM: dumb
+        steps:
+            - add_ssh_keys:
+                fingerprints:
+                    - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
+            - checkout
+            - run:
+                name: Create hash of toolchains
+                command: |
+                    .circleci/create-hash.sh
+            - restore_cache:
+                keys:
+                    - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
+            - restore_cache:
+                keys:
+                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
+            - run:
+                name: Building the tracegen subproject using Verilator
+                command: .circleci/do-rtl-build.sh tracegen
+                no_output_timeout: 120m
+            - save_cache:
+                key: tracegen-{{ .Branch }}-{{ .Revision }}
+                paths:
+                    - "/home/riscvuser/project"
    prepare-firesim:
        docker:
            - image: riscvboom/riscvboom-images:0.0.12
@@ -487,6 +516,30 @@ jobs:
            - run:
                name: Run hwacha tests
                command: .circleci/run-tests.sh hwacha
+    tracegen-run-tests:
+        docker:
+            - image: riscvboom/riscvboom-images:0.0.12
+        environment:
+            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
+            TERM: dumb
+        steps:
+            - checkout
+            - run:
+                name: Create hash of toolchains
+                command: |
+                    .circleci/create-hash.sh
+            - restore_cache:
+                keys:
+                    - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
+            - restore_cache:
+                keys:
+                    - tracegen-{{ .Branch }}-{{ .Revision }}
+            - restore_cache:
+                keys:
+                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
+            - run:
+                name: Run tracegen tests
+                command: .circleci/run-tests.sh tracegen
    firesim-run-tests:
        docker:
            - image: riscvboom/riscvboom-images:0.0.12
@@ -605,6 +658,11 @@ workflows:
                    - install-esp-toolchain
                    - install-verilator

+            - prepare-tracegen:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
            - prepare-firesim:
                requires:
                    - install-riscv-toolchain
@@ -644,6 +702,10 @@ workflows:
                requires:
                    - prepare-hwacha

+            - tracegen-run-tests:
+                requires:
+                    - prepare-tracegen
+
            # Run the firesim tests
            - firesim-run-tests:
                requires:
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -47,5 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
 mapping["rocketchip"]="SUB_PROJECT=rocketchip"
 mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
 mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig"
+mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config"
 mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
 mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
--- a/.circleci/run-tests.sh
+++ b/.circleci/run-tests.sh
@@ -24,6 +24,10 @@ run_both () {
    run_asm $@
 }

+run_tracegen () {
+    make tracegen -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@
+}
+
 case $1 in
    example)
        run_bmark ${mapping[$1]}
@@ -46,6 +50,9 @@ case $1 in
        export PATH=$RISCV/bin:$PATH
        make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]}
        ;;
+    tracegen)
+        run_tracegen ${mapping[$1]}
+        ;;
    *)
        echo "No set of tests for $1. Did you spell it right?"
        exit 1
--- a/.gitmodules
+++ b/.gitmodules
@@ -95,3 +95,6 @@
 [submodule "toolchains/qemu"]
 	path = toolchains/qemu
 	url = https://github.com/qemu/qemu.git
+[submodule "tools/axe"]
+	path = tools/axe
+	url = https://github.com/CTSRD-CHERI/axe.git
--- a/common.mk
+++ b/common.mk
@@ -125,3 +125,23 @@ $(output_dir)/%.out: $(output_dir)/% $(sim)
 ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
 -include $(build_dir)/$(long_name).d
 endif
+
+#################################################
+# Rules for running and checking tracegen tests #
+#################################################
+
+AXE_DIR=$(base_dir)/tools/axe/src
+AXE=$(AXE_DIR)/axe
+
+$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh
+	cd $(AXE_DIR) && ./make.sh
+
+$(output_dir)/tracegen.out: $(sim)
+	mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none 2> $@
+
+$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE)
+	$(base_dir)/scripts/check-tracegen.sh $< > $@
+
+tracegen: $(output_dir)/tracegen.result
+
+.PHONY: tracegen
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -18,6 +18,7 @@ import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import firesim.util.RegisterBridgeBinder
+import tracegen.HasTraceGenTilesModuleImp

 class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
  target.debug.clockeddmi.foreach({ cdmi =>
@@ -64,6 +65,11 @@ class WithTracerVBridge extends RegisterBridgeBinder({
  case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
 })

+class WithTraceGenBridge extends RegisterBridgeBinder({
+  case target: HasTraceGenTilesModuleImp =>
+    Seq(GroundTestBridge(target.success)(target.p))
+})
+
 // Shorthand to register all of the provided bridges above
 class WithDefaultFireSimBridges extends Config(
  new WithTiedOffDebug ++
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -88,6 +88,7 @@ class WithScalaTestFeatures extends Config((site, here, up) => {

 // FASED Config Aliases. This to enable config generation via "_" concatenation
 // which requires that all config classes be defined in the same package
+class DDR3FRFCFS extends FRFCFS16GBQuadRank
 class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB

 // L2 Config Aliases. For use with "_" concatenation
@@ -279,6 +280,7 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
 class FireSimTraceGenConfig extends Config(
  new WithTraceGen(
    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new WithTraceGenBridge ++
  new FireSimRocketChipConfig)

 class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
@@ -316,4 +318,5 @@ class FireSimTraceGenL2Config extends Config(
    nBanks = 4,
    capacityKB = 1024,
    outerLatencyCycles = 50) ++
+  new WithTraceGenBridge ++
  new FireSimRocketChipConfig)
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -88,17 +88,20 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule

 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)

-class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
+class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem
    with HasHierarchicalBusTopology
    with HasTraceGenTiles
    with CanHaveMasterAXI4MemPort {
  override lazy val module = new FireSimTraceGenModuleImp(this)
 }

-class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModuleImp(outer)
+class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer)
    with HasTraceGenTilesModuleImp
    with CanHaveMasterAXI4MemPortModuleImp

+class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness(
+  () => new FireSimTraceGenDUT)
+
 // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
 class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)

--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -138,3 +138,38 @@ class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_Fir
 }
 class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
 class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
+
+abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
+    extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+
+  lazy val generatorArgs = GeneratorArgs(
+    midasFlowKind = "midas",
+    targetDir = "generated-src",
+    topModuleProject = "firesim.firesim",
+    topModuleClass = "FireSimTraceGen",
+    targetConfigProject = "firesim.firesim",
+    targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
+    platformConfigProject = "firesim.firesim",
+    platformConfigs = platformConfig)
+
+  // From HasFireSimGeneratorUtilities
+  // For the firesim utilities to use the same directory as the test suite
+  override lazy val testDir = genDir
+
+  // From TestSuiteCommon
+  val targetTuple = generatorArgs.tupleName
+  val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
+                           s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
+                           s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
+
+  it should "pass" in {
+    assert(make("fsim-tracegen") == 0)
+  }
+}
+
+class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
+  "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
+
+class FireSimL2TraceGenTest extends FireSimTraceGenTest(
+  "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")
--- a/scripts/check-tracegen.sh
+++ b/scripts/check-tracegen.sh
@@ -3,7 +3,7 @@
 set -e

 SCRIPT_DIR=$(dirname $0)
-AXE_DIR=$(realpath ${SCRIPT_DIR}/../../axe)
+AXE_DIR=$(realpath ${SCRIPT_DIR}/../tools/axe)
 ROCKET_DIR=$(realpath ${SCRIPT_DIR}/../generators/rocket-chip)

 TO_AXE=${ROCKET_DIR}/scripts/toaxe.py
--- a/sims/firesim
+++ b/sims/firesim
--- a/tools/axe
+++ b/tools/axe