abejgonzalez
9ea23d43a7
Merge remote-tracking branch 'origin/dev' into local-chisel34
2020-11-15 16:03:25 -08:00
Tim Snyder
1110dd702c
Bump RC, firesim and barstools for chisel3.4 updates
...
Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).
Requires: ucb-bar/barstools#92 and firesim/firesim#658
The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests. You will likely want to bump further.
2020-11-11 18:57:16 +00:00
David Biancolin
80487cc371
Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out}
2020-11-10 11:58:53 -08:00
David Biancolin
230bd81e0e
[firechip] Update legacy firechip config
2020-11-09 09:26:30 -08:00
David Biancolin
08c31014cc
Build out a more complete multiclock example configuration
2020-11-09 09:26:23 -08:00
David Biancolin
4da9e49fc1
[clocking] Fix up() invocations in freq specification fragments
2020-11-09 08:32:25 -08:00
David Biancolin
04cd6b59bd
[clocking] Add a fragment to set bus clock-sink freqs more intuitively
2020-11-09 08:32:19 -08:00
David Biancolin
a559d624df
[clocking] Drive all buses directly from the asyncClockGroup
2020-11-07 21:57:42 -08:00
Abraham Gonzalez
5c5a4b51e3
Merge pull request #710 from ucb-bar/rename-ariane
...
Rename Ariane to CVA6
2020-11-06 14:53:54 -08:00
abejgonzalez
0685812c34
Bump CVA6
2020-11-05 10:30:00 -08:00
abejgonzalez
60cd999002
Bump CVA6 for Make fix
2020-11-04 21:09:24 -08:00
abejgonzalez
59c9163bd5
Bump CVA6 for submodule fixes
2020-11-04 18:37:26 -08:00
abejgonzalez
a2ebbee2ac
Rename Ariane to CVA6
2020-11-04 15:42:30 -08:00
David Biancolin
f504b7a0f5
[clocking] Improve reference clock selection using a multiple-of-fastest strategy
2020-11-03 09:14:55 -08:00
David Biancolin
aa4a44925e
[clocking] Add ScalaTests for the divider-only PLL configurator
2020-11-03 09:14:55 -08:00
David Biancolin
f387634a41
[clocking] Bound SimplePllConfiguration by maximum reference freq
2020-11-03 09:14:55 -08:00
David Biancolin
946a191221
[clocking] Provide a default div for ClockDividerN sv implementation ( #706 )
2020-11-03 12:14:18 -05:00
Jerry Zhao
2d010b63f3
Merge branch 'dev' into lazy-iobinders
2020-11-02 10:02:44 -08:00
Jerry Zhao
7b83da054a
Clean up HarnessBinders
2020-10-28 16:18:22 -07:00
Jerry Zhao
f4d70128c0
Remove redundant ChipTop reset synchronizer
2020-10-28 15:37:31 -07:00
Jerry Zhao
93e57ef230
Make the ChipTop reset pin async always
2020-10-26 15:18:34 -07:00
Jerry Zhao
d61b31a6fe
Merge pull request #702 from ucb-bar/multirocc-gemmini
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Add MultiRoCCGemmini config fragment
2020-10-26 10:03:26 -07:00
Fang, Zitao
4fdb9eb6b0
Merge pull request #647 from ucb-bar/verilator-makefile-fix
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Fix Verilator Simulation run-binary-debug Error
2020-10-23 21:54:58 -07:00
Zitao Fang
abbeb2af9e
Fixed comments
2020-10-23 17:00:56 -07:00
Zitao Fang
0c4dcffb0d
Fixed lowercase p bug
2020-10-23 16:39:56 -07:00
Jerry Zhao
ac19117ec5
Add MultiRoCCGemmini config fragment
2020-10-23 15:41:49 -07:00
Jerry Zhao
7a55c55aa3
Fix no-MBUS configs
2020-10-20 01:12:28 -07:00
Jerry Zhao
e0bf907a06
Merge remote-tracking branch 'origin/dev' into lazy-iobinders
2020-10-19 13:22:01 -07:00
Jerry Zhao
f3d666d2b7
Clarify HarnessBinders ClassTag naming
2020-10-19 10:16:44 -07:00
Jerry Zhao
9927231bc4
Support lazy-iobinders
2020-10-17 22:47:50 -07:00
David Biancolin
1b94e7f10c
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
2020-10-16 23:21:20 +00:00
Alon Amid
6eaac63e1b
address PR comments
2020-10-16 06:34:26 +00:00
Albert Magyar
84e0bf7338
Don't annotate cores with FAMEModelAnnotations
2020-10-15 12:25:39 -07:00
David Biancolin
74c1c9d7ab
Punch out reset in AXI4MMIO IOBinder
2020-10-15 11:28:36 -07:00
Alon Amid
2c935b4ad7
pull firesim mem model config into firesim tweaks
2020-10-15 17:07:51 +00:00
Alon Amid
4a317b0cab
differentiate default config package delimiter
2020-10-15 17:07:20 +00:00
David Biancolin
9c8d2948af
[firechip] Fix a broken config
2020-10-14 15:33:32 -07:00
David Biancolin
6aefb73ab5
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
2020-10-14 15:29:00 -07:00
David Biancolin
211c33f996
Address comments in #690
2020-10-14 14:42:45 -07:00
Jerry Zhao
0c46ed1676
Rename testchip_fesvr to testchip_tsi
2020-10-09 09:34:20 -07:00
Jerry Zhao
25129c27ca
Add testchip_fesvr to uncondtionally used resources
2020-10-09 09:27:58 -07:00
Jerry Zhao
d71c3b6357
Unify htif implementation with firesim
2020-10-09 09:27:58 -07:00
David Biancolin
986b5831c8
[clocking] Sketch out a topology that puts the MBUS is a separate domain
2020-10-09 07:23:17 -07:00
David Biancolin
30b278687b
[clocking] Also aggregate clocks in AsyncClockGroup
2020-10-09 07:13:55 -07:00
David Biancolin
392d5b0801
[clocking] Synchronize all output clocks from DividerOnly generator
2020-10-07 09:32:48 -07:00
Zitao Fang
5282965b5b
Filter specified HTIF arguments and plusargs only
2020-10-06 15:50:11 -07:00
Zitao Fang
355e4ba606
Change to filter all arguments that begin with a '-'
2020-10-05 10:49:04 -07:00
Jerry Zhao
3d0022667a
Bump testchipip
2020-10-01 22:43:43 -07:00
Jerry Zhao
b057cfbd8c
Merge remote-tracking branch 'origin/dev' into clocking-features
2020-10-01 20:12:20 -07:00
Jerry Zhao
2db3c90f83
Merge pull request #648 from ucb-bar/sodor-integrate
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Sodor Integration
2020-10-01 17:31:45 -07:00
