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Rename Ariane to CVA6

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This commit is contained in:
abejgonzalez
2020-11-04 15:05:11 -08:00
parent 946a191221
commit a2ebbee2ac
25 changed files with 105 additions and 108 deletions
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2
.circleci/check-commit.sh
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@@ -48,7 +48,7 @@ search () {
done
}
submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
dir="generators"
if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
then

6
.circleci/config.yml
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@@ -234,12 +234,12 @@ jobs:
- run-tests:
group-key: "group-cores"
project-key: "chipyard-boom"
chipyard-ariane-run-tests:
chipyard-cva6-run-tests:
executor: main-env
steps:
- run-tests:
group-key: "group-cores"
project-key: "chipyard-ariane"
project-key: "chipyard-cva6"
timeout: "30m"
chipyard-sodor-run-tests:
executor: main-env
@@ -431,7 +431,7 @@ workflows:
- chipyard-boom-run-tests:
requires:
- prepare-chipyard-cores
- chipyard-ariane-run-tests:
- chipyard-cva6-run-tests:
requires:
- prepare-chipyard-cores
- chipyard-sodor-run-tests:

4
.circleci/defaults.sh
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@@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop"
grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -67,7 +67,7 @@ mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"

2
.circleci/run-tests.sh
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@@ -91,7 +91,7 @@ case $1 in
tracegen-boom)
run_tracegen ${mapping[$1]}
;;
chipyard-ariane)
chipyard-cva6)
make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
;;
chipyard-sodor)

6
.gitmodules vendored
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@@ -113,9 +113,9 @@
[submodule "software/firemarshal"]
path = software/firemarshal
url = https://github.com/firesim/FireMarshal.git
[submodule "generators/ariane"]
path = generators/ariane
url = https://github.com/ucb-bar/ariane-wrapper.git
[submodule "generators/cva6"]
path = generators/cva6
url = git@github.com:ucb-bar/cva6-wrapper.git
[submodule "tools/DRAMSim2"]
path = tools/DRAMSim2
url = https://github.com/firesim/DRAMSim2.git

6
README.md
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@@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
@@ -35,7 +35,7 @@ If used for research, please cite Chipyard by the following publication:
```
@article{chipyard,
author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
journal={IEEE Micro},
title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
year={2020},
@@ -80,6 +80,6 @@ These additional publications cover many of the internal components used in Chip
[rocket-chip]: https://github.com/freechipsproject/rocket-chip
[boom]: https://github.com/riscv-boom/riscv-boom
[firemarshal]: https://github.com/firesim/FireMarshal/
[ariane]: https://github.com/pulp-platform/ariane/
[cva6]: https://github.com/openhwgroup/cva6/
[gemmini]: https://github.com/ucb-bar/gemmini
[nvdla]: http://nvdla.org/

4
build.sbt
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@@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, ariane, nvdla, sodor)
gemmini, icenet, tracegen, cva6, nvdla, sodor)
.settings(commonSettings)
lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
@@ -154,7 +154,7 @@ lazy val boom = conditionalDependsOn(project in file("generators/boom"))
.dependsOn(rocketchip)
.settings(commonSettings)
lazy val ariane = (project in file("generators/ariane"))
lazy val cva6 = (project in file("generators/cva6"))
.dependsOn(rocketchip)
.settings(commonSettings)

4
common.mk
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@@ -47,7 +47,7 @@ HELP_COMMANDS += \
# include additional subproject make fragments
# see HELP_COMPILATION_VARIABLES
#########################################################################################
include $(base_dir)/generators/ariane/ariane.mk
include $(base_dir)/generators/cva6/cva6.mk
include $(base_dir)/generators/tracegen/tracegen.mk
include $(base_dir)/generators/nvdla/nvdla.mk
include $(base_dir)/tools/dromajo/dromajo.mk
@@ -103,7 +103,7 @@ $(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala
$(FIRRTL_FILE) $(ANNO_FILE): generator_temp
@echo "" > /dev/null
# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir)
$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\

4
docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -20,9 +20,9 @@ Processor Cores
An out-of-order RISC-V core.
See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information.
**Ariane Core**
**CVA6 Core**
An in-order RISC-V core written in System Verilog.
See :ref:`Ariane Core` for more information.
See :ref:`CVA6 Core` for more information.
Accelerators
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

70
docs/Customization/Custom-Core.rst
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@@ -6,14 +6,14 @@ Adding a custom core
You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides step-by-step
instructions on how to achieve this.
.. note::
.. note::
RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC.
.. note::
This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately
from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through
This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately
from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through
GitHub issues!
Wrap Verilog Module with Blackbox (Optional)
@@ -30,15 +30,15 @@ This object is derived from``TileParams``, a trait containing the information ne
their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``.
``TileParams`` holds the parameters for the tile, which include parameters for all components in the tile (e.g.
core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile.
They must be implemented as case classes with fields that can be overridden by
other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of
variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred.
core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile.
They must be implemented as case classes with fields that can be overridden by
other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of
variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred.
``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``,
``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``,
where ``TileType`` is the tile class (see the next section).
All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance
of the tile class ``TileType``.
of the tile class ``TileType``.
``TileParams`` (in the file `BaseTile.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala>`_) ,
``InstantiableTileParams`` (in the file `BaseTile.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala>`_),
@@ -88,7 +88,7 @@ contains the following fields:
val nBreakpoints: Int // # of hardware breakpoints supported (in RISC-V debug specs)
val useBPWatch: Boolean // Support hardware breakpoints
val nPerfCounters: Int // # of supported performance counters
val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension
val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension
val haveFSDirty: Boolean // If true, the core will set FS field in mstatus CSR to dirty when appropriate
val misaWritable: Boolean // Support writable misa CSR (like variable instruction bits)
val haveCFlush: Boolean // Rocket specific: enables Rocket's custom instruction extension to flush the cache
@@ -96,7 +96,7 @@ contains the following fields:
val mtvecInit: Option[BigInt] // mtvec CSR (of V extension) initial value
val mtvecWritable: Boolean // If mtvec CSR is writable
// Normally, you don't need to change these values (except lrscCycles)
// Normally, you don't need to change these values (except lrscCycles)
def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs
def hasSupervisorMode: Boolean = useSupervisor || useVM
@@ -113,19 +113,19 @@ contains the following fields:
def eLen(xLen: Int, fLen: Int): Int = xLen max fLen
def vMemDataBits: Int = 0
}
case class FPUParams(
minFLen: Int = 32, // Minimum floating point length (no need to change)
minFLen: Int = 32, // Minimum floating point length (no need to change)
fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported
divSqrt: Boolean = true, // Div/Sqrt operation supported
sfmaLatency: Int = 3, // Rocket specific: Fused multiply-add pipeline latency (single precision)
dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision)
)
Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some
implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore
Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some
implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore
any fields marked "Rocket specific" and use their default values; however, if you need to store additional information
with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of
with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of
creating your own custom fields.
You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format:
@@ -144,14 +144,14 @@ from the parameters in this class for every such class it found.
value may break Chipyard components that rely on them (e.g. an inaccurate indication of supported ISA extension will
result in an incorrect test suite being generated) as well as any custom modules that use them. ALWAYS document any
fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that
would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but
would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but
you should document them if you use them.
Create Tile Class
-----------------
In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System
interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated.
interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated.
See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core,
which specifies the constraints on the core's parameters and the connections with other diplomatic nodes. This class
usually contains Diplomacy/TileLink code only, and Chisel RTL code should not go here.
@@ -167,10 +167,10 @@ which allow the tile to accept external interrupt. A typical tile has the follow
Connect TileLink Buses
----------------------
Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters
Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters
between the core's memory protocol and TileLink within the Tile module.
in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by
Rocket chip:
Rocket chip:
.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
:language: scala
@@ -179,11 +179,11 @@ Rocket chip:
Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate
widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also
provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the
source files in ``generators/rocket-chip/src/main/scala/amba`` for more info.
provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the
source files in ``generators/rocket-chip/src/main/scala/amba`` for more info.
If you are using some other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba``
as the template, but it is not recommended unless you are familiar with TileLink.
as the template, but it is not recommended unless you are familiar with TileLink.
``memAXI4Node`` is an AXI4 master node and is defined as following in our example:
@@ -215,7 +215,7 @@ The implementation class contains the parameterized, actual hardware that depend
framework according to the info provided in the Tile class. This class will normally contains Chisel RTL code. If your
core is in Verilog, you will need to instantiate the black box class that wraps your Verilog implementation and connect it with the buses
and other components. No Diplomacy/TileLink code should be in this class; you should only connect the IO signals in TileLink
interfaces or other diplomatically defined components, which are located in the tile class.
interfaces or other diplomatically defined components, which are located in the tile class.
The implementation class for your core is of the following form:
@@ -234,12 +234,12 @@ If you create an AXI4 node (or equivalents), you will need to connect them to yo
Connect Interrupt
-----------------
Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices.
In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and
Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices.
In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and
call ``decodeCoreInterrupts()`` with the object as the argument. Note that you should call this function in the implementation
class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the ``TileInterrupts`` bundle
we create above. The definition of ``TileInterrupts``
(in the file `Interrupts.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala>`_) is
we create above. The definition of ``TileInterrupts``
(in the file `Interrupts.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala>`_) is
.. code-block:: scala
@@ -247,7 +247,7 @@ we create above. The definition of ``TileInterrupts``
val debug = Bool() // debug interrupt
val mtip = Bool() // Machine level timer interrupt
val msip = Bool() // Machine level software interrupt
val meip = Bool() // Machine level external interrupt
val meip = Bool() // Machine level external interrupt
val seip = usingSupervisor.option(Bool()) // Valid only if supervisor mode is supported
val lip = Vec(coreParams.nLocalInterrupts, Bool()) // Local interrupts
}
@@ -261,7 +261,7 @@ Here is an example on how to connect these signals in the implementation class:
Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications``
from the implementation class:
(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file
(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file
`Interrupts.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala>`_)
.. code-block:: scala
@@ -290,12 +290,12 @@ the current config. An example of such config will be like this:
:end-before: DOC include end: Config fragment
Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``.
This config fragment simply appends new tile parameters to the end of this list.
This config fragment simply appends new tile parameters to the end of this list.
Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions
in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`.
You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports).
You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports).
If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala``
provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
interface with the memory coherency system.
If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/CVA6Tile.scala``
provides a concrete example of the CVA6 core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
interface with the memory coherency system.

10
docs/Generators/Ariane.rst → docs/Generators/CVA6.rst
View File

@@ -1,14 +1,14 @@
Ariane Core
CVA6 Core
====================================
`Ariane <https://github.com/pulp-platform/ariane>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`.
`CVA6 <https://github.com/openhwgroup/cva6>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
.. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters).
While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
.. Warning:: This target does not support Verilator simulation at this time. Please use VCS.
For more information, please refer to the `GitHub repository <https://github.com/pulp-platform/ariane>`__.
For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.

2
docs/Generators/index.rst
View File

@@ -27,7 +27,7 @@ so changes to the generators themselves will automatically be used when building
TestChipIP
SiFive-Generators
SHA3
Ariane
CVA6
NVDLA
Sodor

1
generators/ariane

Submodule generators/ariane deleted from 3a2eed602f

4
generators/chipyard/src/main/scala/ConfigFragments.scala
View File

@@ -21,7 +21,7 @@ import hwacha.{Hwacha}
import gemmini.{Gemmini, GemminiConfigs}
import boom.common.{BoomTileAttachParams}
import ariane.{ArianeTileAttachParams}
import cva6.{CVA6TileAttachParams}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
@@ -120,7 +120,7 @@ class WithTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true))
case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true))
case other => other
}

3
generators/chipyard/src/main/scala/TestSuites.scala
View File

@@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams}
import freechips.rocketchip.config.{Parameters, Field, Config}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
import boom.common.{BoomTileAttachParams}
import ariane.{ArianeTileAttachParams}
/**
* A set of pre-chosen regression tests
*/

19
generators/chipyard/src/main/scala/config/ArianeConfigs.scala
View File

@@ -1,19 +0,0 @@
package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
// ---------------------
// Ariane Configs
// ---------------------
class ArianeConfig extends Config(
new ariane.WithNArianeCores(1) ++ // single Ariane core
new chipyard.config.AbstractConfig)
class dmiArianeConfig extends Config(
new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new ariane.WithNArianeCores(1) ++ // single Ariane core
new chipyard.config.AbstractConfig)

19
generators/chipyard/src/main/scala/config/CVA6Configs.scala Normal file
View File

@@ -0,0 +1,19 @@
package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
// ---------------------
// CVA6 Configs
// ---------------------
class CVA6Config extends Config(
new cva6.WithNCVA6Cores(1) ++ // single CVA6 core
new chipyard.config.AbstractConfig)
class dmiCVA6Config extends Config(
new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new cva6.WithNCVA6Cores(1) ++ // single CVA6 core
new chipyard.config.AbstractConfig)

14
generators/chipyard/src/main/scala/example/TutorialTile.scala
View File

@@ -16,7 +16,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._
// Example parameter class copied from Ariane, not included in documentation but for compile check only
// Example parameter class copied from CVA6, not included in documentation but for compile check only
// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
// out what parameters you need before you write the parameter class
case class MyCoreParams(
@@ -127,9 +127,9 @@ class MyTile(
// TODO: Create TileLink nodes and connections here.
// DOC include end: Tile class
// DOC include start: AXI4 node
// # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more.
// # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more.
val idBits = 4
val memAXI4Node = AXI4MasterNode(
Seq(AXI4MasterPortParameters(
@@ -160,17 +160,17 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
// TODO: Create the top module of the core and connect it with the ports in "outer"
// If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like
// val core = Module(new MyCoreBlackbox(params...))
// If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like
// val core = Module(new MyCoreBlackbox(params...))
// (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
// (link on the top of the page) for more info.
// You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
// You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala
// for a Verilog example.
// If your core is in Chisel, you can simply instantiate the top module here like other Chisel module
// and connect appropriate signal. You can even implement this class as your top module.
// See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and
// https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for
// https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for
// Chisel example.
// DOC include end: Implementation class

1
generators/cva6 Submodule

Submodule generators/cva6 added at 27157f7bbd

2
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -22,7 +22,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio
import firesim.bridges._
import firesim.configs.MemModelKey
import tracegen.{TraceGenSystemModuleImp}
import ariane.ArianeTile
import cva6.CVA6Tile
import boom.common.{BoomTile}
import barstools.iocell.chisel._

8
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -128,7 +128,7 @@ class FireSimQuadRocketConfig extends Config(
new chipyard.QuadRocketConfig)
// A stripped down configuration that should fit on all supported hosts.
// Flat to avoid having to reorganize the config class hierarchy to remove certain features
// Flat to avoid having to reorganize the config class hierarchy to remove certain features
class FireSimSmallSystemConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
@@ -188,13 +188,13 @@ class SupernodeFireSimRocketConfig extends Config(
new FireSimRocketConfig)
//**********************************************************************************
//* Ariane Configurations
//* CVA6 Configurations
//*********************************************************************************/
class FireSimArianeConfig extends Config(
class FireSimCVA6Config extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.ArianeConfig)
new chipyard.CVA6Config)
//**********************************************************************************
//* Multiclock Configurations

2
generators/firechip/src/test/scala/ScalaTestSuite.scala
View File

@@ -110,7 +110,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite(
"FireSimMulticlockRocketConfig",
"WithSynthAsserts_BaseF1Config")
class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config")
// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
class CITests extends Suites(

10
scripts/tutorial-patches/build.sbt.patch
View File

@@ -3,24 +3,24 @@ index 5d642c1..56f6fda 100644
--- a/build.sbt
+++ b/build.sbt
@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/"))
lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+// sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, ariane, nvdla, sodor)
gemmini, icenet, tracegen, cva6, nvdla, sodor)
.settings(commonSettings)
@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane"))
@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6"))
.dependsOn(rocketchip)
.settings(commonSettings)
-lazy val sha3 = (project in file("generators/sha3"))
- .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
- .settings(commonSettings)
+//lazy val sha3 = (project in file("generators/sha3"))
+// .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+// .settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(rocketchip, chisel_testers, testchipip)

2
sims/firesim

Submodule sims/firesim updated: 1c76c446da...57efb2ec03

8
sims/verilator/Makefile
View File

@@ -91,7 +91,7 @@ VERILATOR_OPT_FLAGS := \
--output-split 10000 \
--output-split-cfuncs 100
# default flags added for external IP (ariane/NVDLA)
# default flags added for external IP (cva6/NVDLA)
VERILOG_IP_VERILATOR_FLAGS := \
--unroll-count 256 \
-Wno-PINCONNECTEMPTY \
@@ -103,14 +103,14 @@ VERILOG_IP_VERILATOR_FLAGS := \
-Wno-style \
-Wall
# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA)
# normal flags used for chipyard builds (that are incompatible with vlog ip aka cva6/NVDLA)
CHIPYARD_VERILATOR_FLAGS := \
--assert
# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used
# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
# NOTE: defer the evaluation of this until it is used!
PLATFORM_OPTS = $(shell \
if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \
then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)