Commit Graph

1190 Commits

Author SHA1 Message Date
Albert Magyar
c2c9bc83de Merge pull request #552 from ucb-bar/no-midas-sub
Don't try to init nonexistent midas submodule
2020-05-20 20:26:41 -07:00
Albert Magyar
7208ab0b68 Don't try to init nonexistent midas submodule 2020-05-20 14:03:39 -07:00
Abraham Gonzalez
b1c59ba2c0 Merge pull request #559 from ucb-bar/nvdla-sw-cleanup
Remove un-needed nested NVDLA submodule
2020-05-20 12:18:39 -07:00
Abraham Gonzalez
6903172e9b Merge pull request #560 from ucb-bar/toolchain-fix
Remove Dromajo build from build-toolchains.sh
2020-05-20 11:50:41 -07:00
abejgonzalez
d2060947b6 bump toolchain version | fix git submodule update 2020-05-19 21:21:10 -07:00
abejgonzalez
0d087b6d32 add auto-gen comments | git init dromajo dir 2020-05-19 19:42:13 -07:00
alonamid
9c73037e93 Version Upgrade Docs Notes (#545)
* version upgrade notes

* [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

* [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

* [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

* [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

* [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2020-05-19 19:09:53 -07:00
abejgonzalez
dfc6c9ae5d bump nvdla workload for one less submodule [ci skip] 2020-05-19 16:20:56 -07:00
David Biancolin
dca6604cf4 Merge pull request #554 from ucb-bar/generator-unification-p1
Have FireChip use the standard Chipyard generator
2020-05-19 15:52:20 -07:00
Abraham Gonzalez
eb4df795e1 Merge pull request #557 from ucb-bar/update-issues
small cleanup to issues
2020-05-19 15:36:20 -07:00
abejgonzalez
0fc5a54096 small cleanup to issues [ci skip] 2020-05-19 12:13:05 -07:00
David Biancolin
dcf92ae15b Merge remote-tracking branch 'origin/dev' into generator-unification-p1 2020-05-19 18:53:08 +00:00
David Biancolin
7f3ae32e33 Bump FireSim 2020-05-19 01:00:25 +00:00
David Biancolin
fa2d620fb2 Remove commented code in ScalaTests 2020-05-19 00:50:14 +00:00
Abraham Gonzalez
178911e457 Merge pull request #553 from ucb-bar/misc-cleanup
Dromajo + TraceIO Cleanup
2020-05-18 12:24:56 -07:00
David Biancolin
db65105163 Bump FireSim 2020-05-18 19:23:16 +00:00
abejgonzalez
465e96a5ca bump testchipip 2020-05-18 12:21:17 -07:00
David Biancolin
96e838c773 [firechip] Set the cover property library in FireSim Harnesses 2020-05-17 00:18:54 +00:00
David Biancolin
99846c1ccb [firechip] Use the standard Chipyard generator 2020-05-17 00:18:17 +00:00
abejgonzalez
e913ddbbbe [traceio] bump testchipip 2020-05-16 16:45:50 -07:00
David Biancolin
8d5927913f [stage] Support using Chipyard's stage for non-processor designs 2020-05-16 22:49:06 +00:00
David Biancolin
73f8ec5017 [stage] Make config concatenation actually work 2020-05-16 22:49:06 +00:00
abejgonzalez
d88627e913 [traceio] bump firesim 2020-05-16 14:51:27 -07:00
abejgonzalez
9dda27f20c [traceio] wdata: use option instead of 1.B wire 2020-05-16 14:47:15 -07:00
abejgonzalez
ca3c557fe2 [dromajo] change dromajo url | small cleanup 2020-05-16 13:43:14 -07:00
abejgonzalez
33e83e0644 [dromajo] separate documentation | move header file gen to tcip 2020-05-16 13:08:57 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
John Wright
7c7b336c3f Add SPI flash support (#546)
* Add SPI flash configs, IOBinders, CI tests, and docs

* Add writable SPI flash support

* bump

* Fix CI

* Fix CI

* Update docs/Generators/TestChipIP.rst

Co-authored-by: Chick Markley <chick@qrhino.com>

* Maybe actually fix CI

* Fix broken merge

* Fix the tutorial patch

* bump tcip to master

* fix GPIO naming bug

Co-authored-by: Chick Markley <chick@qrhino.com>
2020-05-14 19:19:50 -07:00
David Biancolin
1b1f477619 Merge pull request #551 from ucb-bar/firrtl-test-jar
Assemble the firrtl-test.jar and put it in its own directory
2020-05-14 17:30:52 -07:00
David Biancolin
ebe993cefe Assemble the firrt-test.jar and put it in its own directory 2020-05-14 19:25:21 +00:00
alonamid
3e57a5f539 Merge pull request #544 from ucb-bar/firrtl-1.3-RC-bump
Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3
2020-05-13 16:39:50 -07:00
abejgonzalez
460455e790 extend midas examples timeout in ci 2020-05-13 13:18:06 -07:00
alonamid
3fc205997f bump treadle to master 2020-05-13 11:41:21 -07:00
alonamid
de617d16ed bump firesim with firrtl 1.3 2020-05-13 11:31:40 -07:00
alonamid
ab8f737540 Merge branch 'firrtl-1.3-RC-bump' of https://github.com/ucb-bar/chipyard into firrtl-1.3-RC-bump 2020-05-13 10:40:55 -07:00
alonamid
afb6518ec2 bump barstools to master with firrtl 1.3 2020-05-13 10:40:02 -07:00
Albert Magyar
d5c1ad4c1f Bump barstools 2020-05-13 10:38:23 -07:00
alonamid
f0389bbe66 bump boom and ariane to master with RC firrtl 1.3 2020-05-13 10:03:30 -07:00
alonamid
9e95082a8a bump testchipip with buffer arg 2020-05-13 00:10:23 -07:00
alonamid
933d033569 sifive cache bump to RC firrtl 1.3 2020-05-12 23:34:01 -07:00
David Biancolin
6950ad7cee Comment out Ariane from ScalaTests 2020-05-12 22:01:14 +00:00
David Biancolin
d16c57867d Bump FireSim 2020-05-12 22:00:43 +00:00
Albert Magyar
2a6bd3bd5c Bump verilator to v4.034 (#547)
* Bump verilator to v4.034
* Add new flags to verilator makefile
* Conditionally set timescale flag based on Verilator version
2020-05-11 23:02:37 -07:00
David Biancolin
2fa9a41902 [make] Fix firrtl prerequiste lookup 2020-05-11 03:46:03 +00:00
David Biancolin
57c840f2ab Merge pull request #549 from ucb-bar/silence-http-warning
[SBT] Hush up scalasbt resolver http complaint
2020-05-09 11:46:06 -07:00
David Biancolin
0bdf39ffe4 [SBT] Hush up scalasbt resolver http complaint 2020-05-09 04:21:49 +00:00
Colin Schmidt
596925020f Connect debug clocks when debug is tied off 2020-05-07 11:24:17 -07:00
Colin Schmidt
3c18880064 Increase verilator reset length 2020-05-06 18:39:42 -07:00
Albert Magyar
006ecd2b7c Basic changes to barstools to get sim to compile 2020-05-06 21:46:25 +00:00