config: reduce Radiance shared memory to 32 KiB

.gitmodules

@@ -87,22 +87,22 @@
 	url = https://github.com/ucb-bar/libgloss-htif.git
 [submodule "toolchains/riscv-tools/riscv-isa-sim"]
 	path = toolchains/riscv-tools/riscv-isa-sim
-	url = https://gh-proxy.org/https://github.com/richardyrh/riscv-isa-sim
+	url = https://github.com/richardyrh/riscv-isa-sim
 [submodule "toolchains/riscv-tools/riscv-openocd"]
 	path = toolchains/riscv-tools/riscv-openocd
-	url = https://gh-proxy.org/https://github.com/riscv/riscv-openocd.git
+	url = https://github.com/riscv/riscv-openocd.git
 [submodule "toolchains/riscv-tools/riscv-pk"]
 	path = toolchains/riscv-tools/riscv-pk
-	url = https://gh-proxy.org/https://github.com/riscv-software-src/riscv-pk.git
+	url = https://github.com/riscv-software-src/riscv-pk.git
 [submodule "toolchains/riscv-tools/riscv-spike-devices"]
 	path = toolchains/riscv-tools/riscv-spike-devices
-	url = https://gh-proxy.org/https://github.com/ucb-bar/spike-devices.git
+	url = https://github.com/ucb-bar/spike-devices.git
 [submodule "toolchains/riscv-tools/riscv-tests"]
 	path = toolchains/riscv-tools/riscv-tests
-	url = https://gh-proxy.org/https://github.com/riscv-software-src/riscv-tests.git
+	url = https://github.com/riscv-software-src/riscv-tests.git
 [submodule "toolchains/riscv-tools/riscv-tools-feedstock"]
 	path = toolchains/riscv-tools/riscv-tools-feedstock
-	url = https://gh-proxy.org/https://github.com/ucb-bar/riscv-tools-feedstock.git
+	url = https://github.com/ucb-bar/riscv-tools-feedstock.git
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git
@@ -159,4 +159,4 @@
   url = https://github.com/ucb-bar/compress-acc.git
 [submodule "generators/radiance"]
 	path = generators/radiance
-	url = https://git.nudt.space/wu-arch/radiance.git
+	url = https://github.com/ucb-bar/radiance.git

generators/chipyard/src/main/scala/config/RadianceConfigs.scala

@@ -25,9 +25,10 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
 // aliases for virgo
 class VirgoConfig extends RadianceClusterConfig
 class VirgoFP16Config extends RadianceFP16ClusterConfig
+class VirgoVoltaConfig extends RadianceFP16ClusterConfig
+class VirgoAmpereConfig extends RadianceFP16ClusterConfig
 class VirgoHopperConfig extends Radiance4CFP16ClusterConfig
 class VirgoBlackwellConfig extends RadianceBlackwellClusterConfig
-class VirgoBlackwellSynConfig extends RadianceBlackwellClusterSynConfig
 class VirgoFlashConfig extends RadianceClusterConfig
 class VirgoSynConfig extends RadianceClusterSynConfig
 class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig
@@ -36,7 +37,7 @@ class VirgoHopperSynConfig extends Radiance4CFP16ClusterSynConfig
 class RadianceBaseConfig extends Config(
   // NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in
   // the verilog source as well!
-  new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++
+  new radiance.subsystem.WithSimtConfig(nWarps = 4, nCoreLanes = 4, nMemLanes = 4, nSrcIds = 32) ++
   new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
   new WithExtMemSize(BigInt("80000000", 16)) ++
   new WithRadBootROM() ++
@@ -57,7 +58,7 @@ class RadianceBaseConfig extends Config(
 
 class RadianceFP16ClusterConfig extends Config(
   new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
-  new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++
+  new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++
   new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 16) ++
   new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
   new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
@@ -75,7 +76,7 @@ class Radiance8B8WFP16ClusterConfig extends Config(
 
 class Radiance4CFP16ClusterConfig extends Config(
   new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
-  new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = true, useVxCache = false) ++
+  new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = true, useVxCache = false) ++
   // new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 16,
   //                                              memType = radiance.subsystem.TwoReadOneWrite,
   //                                              serializeUnaligned = radiance.subsystem.CoreSerialized) ++
@@ -89,18 +90,17 @@ class Radiance4CFP16ClusterConfig extends Config(
 
 class RadianceBlackwellClusterConfig extends Config(
   new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
-  new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, tensorCoreBlackwell = true, numTensorWarps = 2, startupAddress = BigInt("80000000", 16), useVxCache = false) ++
+  new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, tensorCoreBlackwell = true, startupAddress = BigInt("80000000", 16), useVxCache = false) ++
   new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 8) ++
   new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
   new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
   new radiance.subsystem.WithRadianceCluster(0) ++
-  new radiance.subsystem.WithSimtConfig(nWarps = 4, nCoreLanes = 4, nMemLanes = 4, nSrcIds = 32) ++
   new RadianceBaseConfig)
 
 class RadianceClusterConfig extends Config(
   // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
   new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
-  new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = false, tensorCoreDecoupled = false, useVxCache = false) ++
+  new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = false, tensorCoreDecoupled = false, useVxCache = false) ++
   // new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++
   new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10/*KBytes*/, numBanks = 8, numWords = 8,
                                                // memType = radiance.subsystem.TwoReadOneWrite,
@@ -153,10 +153,6 @@ class Radiance4CFP16ClusterSynConfig extends Config(
   new radiance.subsystem.WithRadianceSimParams(false) ++
     new Radiance4CFP16ClusterConfig)
 
-class RadianceBlackwellClusterSynConfig extends Config(
-  new radiance.subsystem.WithRadianceSimParams(false) ++
-    new RadianceBlackwellClusterConfig)
-
 class RadianceBigLittleClusterSynConfig extends Config(
   new radiance.subsystem.WithRadianceSimParams(false) ++
     new RadianceBigLittleClusterConfig)

sims/verilator/Makefile

@@ -104,9 +104,8 @@ get_waveform_flag = +vcdfile=$(1).$(if $(filter $(USE_FST),0),vcd,fst)
 #----------------------------------------------------------------------------------------
 # we initially had --noassert for performance, but several modules use
 # assertions, including dramsim, so we enable --assert by default
-VERILATOR_OUTPUT_SPLIT ?= 2000
-VERILATOR_OUTPUT_SPLIT_CFUNCS ?= 20
-VERILATOR_OUTPUT_GROUPS ?= 0
+VERILATOR_OUTPUT_SPLIT ?= 10000
+VERILATOR_OUTPUT_SPLIT_CFUNCS ?= 100
 
 VERILATOR_OPT_FLAGS ?= \
 	-O0 \
@@ -170,7 +169,6 @@ VERILATOR_NONCC_OPTS = \
 VERILATOR_CXXFLAGS = \
 	$(SIM_CXXFLAGS) \
 	$(RUNTIME_PROFILING_CFLAGS) \
-	-O0 \
 	-fno-inline \
 	-DVERILATOR
 
@@ -201,23 +199,25 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
 # build makefile fragment that builds the verilator sim rules
 #########################################################################################
 $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
+	rm -rf $(model_dir)
 	mkdir -p $(model_dir)
-	$(VERILATOR) -j $(VERILATOR_MAKE_JOBS) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
+	$(VERILATOR) -j 36 $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
 	touch $@
 
 $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
+	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
-	$(VERILATOR) -j $(VERILATOR_MAKE_JOBS) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
+	$(VERILATOR) -j 36 $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
 	touch $@
 
 #########################################################################################
 # invoke make to make verilator sim rules
 #########################################################################################
 $(sim): $(model_mk) $(dramsim_lib)
-	$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O0 OPT_SLOW=-O0 OPT_GLOBAL=-O0 -C $(model_dir) -f V$(TB).mk
+	$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
 
 $(sim_debug): $(model_mk_debug) $(dramsim_lib)
-	$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O0 OPT_SLOW=-O0 OPT_GLOBAL=-O0 -C $(model_dir_debug) -f V$(TB).mk
+	$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
 
 #########################################################################################
 # create a verilator vpd rule