120 lines
3.0 KiB
Makefile
120 lines
3.0 KiB
Makefile
# See LICENSE for license details.
|
|
|
|
# Required variables:
|
|
# - MODEL
|
|
# - PROJECT
|
|
# - CONFIG_PROJECT
|
|
# - CONFIG
|
|
# - BUILD_DIR
|
|
# - FPGA_DIR
|
|
|
|
# Optional variables:
|
|
# - EXTRA_FPGA_VSRCS
|
|
|
|
# export to bootloader
|
|
export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
|
|
|
|
# export to fpga-shells
|
|
export FPGA_TOP_SYSTEM=$(MODEL)
|
|
export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
|
|
export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
|
|
export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
|
|
|
|
export BUILD_DIR
|
|
|
|
EXTRA_FPGA_VSRCS ?=
|
|
PATCHVERILOG ?= ""
|
|
BOOTROM_DIR ?= ""
|
|
|
|
base_dir=$(abspath ..)
|
|
export rocketchip_dir := $(base_dir)/generators/rocket-chip
|
|
SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10
|
|
SBT_PROJECT ?= chipyard
|
|
firrtl_dir := $(base_dir)/tools/firrtl
|
|
|
|
# Build firrtl.jar and put it where chisel3 can find it.
|
|
FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
|
|
FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
|
|
|
|
$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala")
|
|
$(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala
|
|
mkdir -p $(base_dir)/lib
|
|
cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR)
|
|
|
|
# Build .fir
|
|
long_name := $(CONFIG_PROJECT).$(CONFIG)
|
|
firrtl := $(BUILD_DIR)/$(long_name).fir
|
|
$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR)
|
|
mkdir -p $(dir $@)
|
|
cd $(base_dir) && $(SBT) "project freedomPlatforms" \
|
|
"runMain chipyard.Generator \
|
|
--target-dir $(BUILD_DIR) \
|
|
--name $(long_name) \
|
|
--top-module $(PROJECT).$(MODEL) \
|
|
--legacy-configs $(CONFIG_PROJECT).$(CONFIG)"
|
|
|
|
.PHONY: firrtl
|
|
firrtl: $(firrtl)
|
|
|
|
# Build .v
|
|
verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
|
|
$(verilog): $(firrtl) $(FIRRTL_JAR)
|
|
$(FIRRTL) -i $(firrtl) -o $@ -X verilog
|
|
ifneq ($(PATCHVERILOG),"")
|
|
$(PATCHVERILOG)
|
|
endif
|
|
|
|
.PHONY: verilog
|
|
verilog: $(verilog)
|
|
|
|
romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
|
|
$(romgen): $(verilog)
|
|
ifneq ($(BOOTROM_DIR),"")
|
|
$(MAKE) -C $(BOOTROM_DIR) romgen
|
|
mv $(BUILD_DIR)/rom.v $@
|
|
endif
|
|
|
|
.PHONY: romgen
|
|
romgen: $(romgen)
|
|
|
|
f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
|
|
$(f):
|
|
echo $(VSRCS) > $@
|
|
|
|
bit := $(BUILD_DIR)/obj/$(MODEL).bit
|
|
$(bit): $(romgen) $(f)
|
|
cd $(BUILD_DIR); vivado \
|
|
-nojournal -mode batch \
|
|
-source $(fpga_common_script_dir)/vivado.tcl \
|
|
-tclargs \
|
|
-top-module "$(MODEL)" \
|
|
-F "$(f)" \
|
|
-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
|
|
-board "$(BOARD)"
|
|
|
|
|
|
# Build .mcs
|
|
mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
|
|
$(mcs): $(bit)
|
|
cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
|
|
|
|
.PHONY: mcs
|
|
mcs: $(mcs)
|
|
|
|
# Build Libero project
|
|
prjx := $(BUILD_DIR)/libero/$(MODEL).prjx
|
|
$(prjx): $(verilog)
|
|
cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)"
|
|
|
|
.PHONY: prjx
|
|
prjx: $(prjx)
|
|
|
|
# Clean
|
|
.PHONY: clean
|
|
clean:
|
|
ifneq ($(BOOTROM_DIR),"")
|
|
$(MAKE) -C $(BOOTROM_DIR) clean
|
|
endif
|
|
$(MAKE) -C $(FPGA_DIR) clean
|
|
rm -rf $(BUILD_DIR)
|