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chipyard
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0656c5da4f0e99e0be5a4a18626a96c6462f5006
chipyard
/
fpga
History
abejgonzalez
0656c5da4f
First pass on using CY make system
2020-09-03 20:29:19 -07:00
..
bootrom
/xip
First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
2020-09-02 12:48:44 -07:00
fpga-shells
@
e8e7f8a321
First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
2020-09-02 12:48:44 -07:00
src/main/scala
/arty
First pass on using CY make system
2020-09-03 20:29:19 -07:00
common.mk
First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
2020-09-02 12:48:44 -07:00
Makefile
First pass on using CY make system
2020-09-03 20:29:19 -07:00
Makefile.e300artydevkit
First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
2020-09-02 12:48:44 -07:00