30 lines
1.4 KiB
ReStructuredText
30 lines
1.4 KiB
ReStructuredText
.. _advanced-usage:
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Advanced Usage
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==============
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Alternative RTL Flows
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---------------------
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The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
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.. code-block:: shell
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export CUSTOM_VLOG=<your verilog files>
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export VLSI_TOP=<your top module>
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Manual Step Execution & Dependency Tracking
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-------------------------------------------
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It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
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Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``.
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Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
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.. code-block:: shell
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make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
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Simulation
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----------
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With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design.
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